Physical Constraints

DDR memory controllers can be placed only in the pre-defined locations that are optimized for maximum performance. The maximum width of the DDR memory varies based on die/package combination and placement. For information about the DDR placement, see the respective PPATs as follows:

The DDR subsystem location is selected using the physical design constraint (PDC) or the I/O Editor. Libero assigns the I/Os based on the selection of the DDR memory location. Before placing the DDR subsystem to the required I/O Bank location, the VDDI and VREF of that I/O Bank must be set to the appropriate value. In I/O Editor, the VDDI and VREF are set using the I/O Bank Settings option.