Controller Options

DDR subsystem features are set using the Controller tab, as shown in Figure 1.

Table 1. Supported AXI Bus Data Width
DQ Width Supported AXI Data Bus Width
x16 64, 128
x32 64, 128, 256
x64 512
Table 2. AXI Address Mapping
AXI Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Column Address                                       C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0    
Bank Address                                 BA2 BA1 BA0                          
Row Address       R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0                                
Note: The address mapping shown in the preceding table is applicable to Native interface also.
Figure 1. DDR Configurator—Controller Options