DDR subsystem features are set using the Controller tab, as shown in Figure 1.
- Instance Select—enables selection of the DDR subsystem instance number that is used to unify the controller instance. PolarFire and PolarFire SoC devices support a maximum of six DDR subsystem instances.
- User Interface—options are AMBA AXI3/4 and native interface. The following table lists the supported AXI bus data widths with respect to the DQ widths.
| DQ Width | Supported AXI Data Bus Width |
|---|---|
| x16 | 64, 128 |
| x32 | 64, 128, 256 |
| x64 | 512 |
- Efficiency—provides control over memory refresh, precharge, and address ordering options. Queue depth can be set to 3 or 4 for DDR3 using the Command queue depth option on DDR Configurator > Controller tab.
- Data Bus Turnaround—provides additional bus turnaround time between different SDRAM ranks. The turnaround time is the number of clock cycles it takes to change the access from one rank to another rank for back-to-back memory accesses (read to read, read to write, write to write, and write to read). The AXI interface address is mapped based on the type of the Address Ordering selected in the PF_DDR3 configurator. For example, if Chip-Row-Bank-Col is selected, and if a row address width and column address width is configured for 13 and 11, the AXI address is mapped as shown in the following table.
| AXI Address | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Column Address | C10 | C9 | C8 | C7 | C6 | C5 | C4 | C3 | C2 | C1 | C0 | |||||||||||||||||||||
| Bank Address | BA2 | BA1 | BA0 | |||||||||||||||||||||||||||||
| Row Address | R12 | R11 | R10 | R9 | R8 | R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0 |
Note: The address mapping shown in the preceding table is applicable to Native interface
also.
- Misc—provides the following options:
- Enable RE-INIT Controls—when selected, the configurator exposes the CTRLR_INIT signal. Initialization begins when a low-to-high transition is detected on this signal.
- ODT activation settings on read/write—provides options to enable ODT on read and write operations.
Figure 1. DDR Configurator—Controller Options
