This section describes the PHY top-level pin list and how they interconnect to other modules in a DDR subsystem. The DDR3 PHY is compliant with DFI 3.1 and can be easily integrated with controllers that comply with DFI 3.1. All of the pin list, description, behavior, and timing are as per DFI 3.1. For more information, see the DFI 3.1 specification.
The following figure shows how PHY integrates with a memory controller for control, write and read interfaces.
Figure 1. DDR PHY DFI Interface
The following figure shows how the training IP inside the DDR PHY integrates with a memory controller. The training IP includes write calibration.
Figure 2. DDR PHY Training IP Interface with Write Calibration
The following figure shows how DDR PHY interfaces with DRAM, PLL, and Miscellaneous.
Figure 3. DDR PHY Interface with DRAM, PLL, and Miscellaneous
