DDR3 Layout Guidelines

This section describes the routing guidelines for DDR3 interface for PolarFire SoC Family. The guidelines are with reference to maximum x72 data width from signal integrity perspective. All the guidelines are provided considering maximum data rate supported. It is recommended to evaluate the interface by performing system level signal integrity simulations. The user is assumed to have the knowledge of the memory interface guidelines.

Table 1. DDR3 Interface Signals
Clock Signal Description
CK[1:0] P/N Differential clock signals
Control Signals
CS[1:0] Chip select
CKE[1:0] Clock Enable
ODT[1:0] On die termination enable
Reset_n Reset signal
Address Signals
A[12:0] Address Signals
BA[2:0] Bank address
Command Signals
RAS_n Row address select
CAS_n Column address select
WE_n Write enable
Data Signals
DQ[31:0] Data bit
DM[3:0] Data mask
DQS_P/N[8:0] Data strobe

Due to high speed signaling, DDR3 uses fly-by routing topology for Address, Command, Control signals to achieve best performance. As shown in the following section, the ADDR/CMD are routed as single ended in fly-by topology. It is recommended to have all the signals being routed in one signal layer to control the skew within the signal groups. The DQ/DQS signals being point to point signals, uses on die termination on memory and FPGA side.