I/O Lane

An I/O lane contains 12 I/Os, a lane controller, I/O gearing logic, and a set of high-speed, low-skew clock resources. The I/O gearing logic in a lane enables easy data transfer between the high-speed I/O pad and the lower-speed FPGA core. The logic is used to either gear up the data rate from the FPGA fabric to the memory device or gear down the data rate from the memory device to the FPGA fabric. For information about non-memory interface usage, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.

The lane controller contains the logic for managing the read and write DQS signals and provides the lane clocks. The following table lists the number of lanes required for the DDR memory interface.

Table 1. DDR Memory Interface Data Lanes
Memory Type DQ Width Number of I/O Lanes
Address/Command Lanes Data Lanes
DDR3/4 x16 3 2
DDR3/4 x32 3 4
DDR3/4 x40 3 5
DDR3/4 x64 3 8
DDR3/4 x72 3 9
LPDDR3 x16 2 2
LPDDR3 x32 2 4

Each data lane uses one I/O lane with 12 I/O pads each—two of the I/O pads are used for the DQS, eight for the DQ bits, and one for the data mask (DM). One I/O pad is left as spare.

Note: I/O usage depends on the configuration of the DDR memory, not all I/Os in the address/command lanes are used. Some I/Os in these lanes can be reused as normal I/Os. For data lanes, all 12 I/Os in the lane are used.