Sample Read Sequence

The following figure shows a sample read sequence consisting of single read request.

Figure 1. Example Sample Read Sequence

The following points summarize a read sequence:

  1. 1.The L_R_REQ signal is first asserted along with the L_ADDR signal, and the L_B_SIZE signal is set to 32.
  2. 2.In the previous clock cycle, the l_busy signal was not asserted, indicating that the subsystem accepted the first request on that cycle. The L_R_REQ signal remains asserted. The L_ADDR and L_B_SIZE signals are updated for the next read request.
  3. 3.The L_R_REQ signal is deasserted, indicating no other read requests are required.
  4. 4.As a result of the read request, the subsystem asserts the row address (A), bank address (BA), and chip select (CS_N) using the activate command to open the bank at the requested row.
  5. 5.The subsystem issues a read command with a column address corresponding to the request at the respective clock cycle.
  6. 6.The subsystem issues the next read command with the corresponding column address.
  7. 7.Read data begins to appear on the SDRAM bus on the DQ lines.
  8. 8.L_R_VALID is asserted, and read data appears in the native interface.
  9. 9.L_R_VALID is deasserted.

In this sequence, all read requests are to the same bank and row. If the next read was to different banks or rows, the core may have issued precharge and/or activate commands prior to issuing read commands.