Training Logic

The training logic manages the DFI 3.1 training requests between the integrated PHY and DDR controller modules, and performs the following operations.

The CTRLR_READY signal is asserted to indicate the completion of initialization and training. This signal can be monitored from the fabric.

Clock Training

Write Leveling

Write leveling is a training mode used during DRAM initialization. The write leveling process identifies the delay when the write DQS rising edge aligns with the rising edge of REF_CLK. By identifying this delay, the system can accurately align the write DQS within REF_CLK. When it is aligned, data can be written to the SDRAM. This alignment is at the memory chip, not at the I/O Lane.

The fly-by topology introduced in DDR3 improves signal integrity, but it creates variable skew between the CLK and DQS in every DRAM device. Long traces on DIMM can create skew greater than one MEM_CLK cycle.

However, the JEDEC® DDR TDQSS specification requires DQS and CLK to align ± 0.25 
MEM_CLK. Write leveling compensates for this skew. It is the first in a sequence of training steps. The memory controller has a programmable DQS delay. The DRAM provides feedback to indicate if the DQS leads or lags the CLK.

As illustrated in the following figure, the training logic sends out widely spaced DQS pulses. The DRAM uses CLK as D input and DQS as CLK to the flip-flop. The Q output of the flip-flop is fed back to the prime DQ (the DQ bit on which feedback is provided). The prime DQ could be different for different vendors. The objective is to detect a 0-to-1 transition on the CLK with a DQS rising edge. This is done by moving the DQS in small steps until the sampled CLK changes from 0-to-1. When the transition is detected, DQ is aligned with DQS.

Figure 1. DQS Delay

Read Leveling

I/O Calibration

The Fabric DDR subsystem performs DDR memory I/O calibration after device power-up. For more information about I/O calibration, see PolarFire FPGA and PolarFire SoC FPGA Device Power-Up and Resets User Guide.