For DDR4, the Controller tab includes the following additional settings under Efficiency.
- The Address Ordering includes the additional setting
Chip-Row-BG1-Bank-Col-BG0.
This selection will map the LSBs of an address to the BG0 field of the memory. This results in alternating Bank Groups during a burst operation based on the tCCD_S timing parameter (see memory device datasheet for tCCD_S settings). The tCCD_S parameter is the timing parameter which results in a better efficient operation for the DDR IP Configurator in the DDR4 mode.
Figure 1. Address Ordering—Chip-Row-BG1-Bank-Col-BG0
- The Number of banks to look up option includes additional
selections for 8 and 16. The default selection is 4.
This should be set to the number of banks in a Bank Group of the DDR4 memory device being used. Selecting a higher value is more challenging in terms if timing closure on the controller. A setting of 8 works for all but the most congested designs. A setting of 16 works for designs that have 15% timing margin or more.
Figure 2. Number of Banks to Look Up