ZQ Calibration

After the second step, the controller performs the ZQ calibration. This command takes 512 REF_CLK cycles to complete the ZQ calibration. After issuing this command, the controller must wait for 512 REF_CLK cycles. The ZQCL command is issued (by asserting CS_N=0, WE_N=0, and DRAM ADDR=0x400 for DDR3). The controller drives these signals accordingly on the DFI interface.

Figure 1 shows ZQCL on DFI followed by ZQCL on DRAM interface. There is a single timing parameter (tCTRL_DELAY) for all of the control Interface. The latency seen Figure 1 is minimal latency observed from the DFI command to DRAM command. For this example, tCTRL_DELAY was set to 0. Any tCTRL_DELAY value set by the controller is added to the latency shown in Figure 1.

Figure 1. ZQCL On DFI Followed By ZQCL On DRAM INTERFACE