Bank Management

The DDR controller uses various bank management techniques to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to sixteen DDR4 memory banks and eight DDR3/LPDDR3 memory banks can be managed at one time. Read and write requests are issued with minimal idle time between commands, limited only by DDR timing specifications. This timing mechanism results in minimal delay between requests, enabling up to 100% memory throughput for sequential accesses (not including refresh and ZQ calibration commands).