DDR4 Layout Guidelines

This section describes the routing guidelines for DDR4 interface for PolarFire SoC Family. The guidelines are with reference to maximum x72 data width from signal integrity perspective. All the guidelines are provided considering maximum data rate supported. It is recommended to evaluate the interface by performing system level signal integrity simulations. The user is assumed to have the knowledge of the memory interface guidelines.

Table 1. DDR4 Interface Signals
Clock Signals Description
CK[1:0]_P\N Differential Clock signals
Address and Command Signals
A[12:0] Address signals
BA[1:0] Bank Address signals
BG[1:0] Bank Group signals
WE Write Enable
RAS_n Row address strobe
CAS_n Column address strobe
ACT_n Activation Command Input
PAR Command and address parity
Control Signals
CKE Clock Enable
CS_n[1:0] Chip Select
ODT On die termination
Reset Reset
Data Group
DQ[31:0] Data signals
DQS[3:0]_P/N Differential data strobe
DM_N[3:0] Data mask

DDR4 interface on PolarFire SoC supports maximum data rate of 1600 MT/s on HSIO banks. The ADDR/CMD and CK signals are routed in fly-by topology and they are terminated at the last memory component with respect to VDDI/2. The data signals are routed as point to point.