Initialization Sequence

After the asynchronous system reset (SYS_RESET_N) and PLL_LOCK are deasserted, the DDR controller performs a JEDEC compliant initialization sequence for memory devices. Each DDR SDRAM device has a series of mode registers (MR) that are accessed using the mode-register-set (MRS) commands. These mode registers set various SDRAM behaviors, such as burst length, CAS latency, ODT value, additive latency, and so on. These registers can be configured using the DDR Configurator.

The CTRLR_READY signal is asserted to indicate that initialization is completed. This signal can be monitored from the fabric.

The following sections explain the automatic initialization sequence for DDR3, DDR4, and LPDDR3 memory devices.