Accessing DDR Subsystem Through AXI4 Interface

In AXI4 interface mode, the AXI4 master implemented in the FPGA fabric accesses the DDR memory through the AXI4 interconnect and the DDR subsystem, as shown in the following figure.

Figure 1. DDR Subsystem Accessed Through AXI4 Interface

AXI4 interconnect functions in pass-through mode for a single-master-and-slave configuration. The AXI4 interconnect IP (CoreAXI4Interconnect) is available for download from the Libero SoC IP catalog.

After successful DDR initialization, the AXI master initiates reads from and writes to the DDR memory. The following steps describe how to create a design to access the DDR3 memory from the AXI master in the FPGA fabric:

  1. 1.Create a SmartDesign, and instantiate the DDR3 macro.
  2. 2.Configure the DDR3 subsystem as described in Implementation, or apply the preset configuration (if any), as shown in Figure 1. The design shown in this figure is created to access the DDR3 memory with a 32-bit data width through the AXI4 interface.
  3. 3.Instantiate the user AXI4 master logic in the SmartDesign canvas. Ensure that the AXI master logic accesses the DDR3 subsystem only after CTRLR_READY is high.
  4. 4.Instantiate the CoreAXI4Interconnect IP, and configure single master and slave, as shown in the following figure.
    Figure 2. CoreAXI4Interconnect IP Configurator
  5. 5.The AXI master and CoreAXI4Interconnect IP clocks must be driven from the SYS_CLK clock of the DDR3 subsystem.
  6. 6.In the SmartDesign canvas, connect the blocks as shown in the following figure.
    Figure 3. SmartDesign Connection—AXI
  7. 7.Create a new SmartDesign testbench to simulate the design.
  8. 8.Instantiate the top-level design component and the DDR memory simulation models.
  9. 9.Configure CLK_GEN to generate the PLL reference clock, and connect to PLL_REF_CLK.
  10. 10.Connect the blocks in SmartDesign testbench, as shown in the following figure.
    Figure 4. SmartDesign Testbench
  11. 11.Select Simulate from Libero Design Flow -> Verify Pre-synthesized Design.

    The DDR subsystem initializes the memory model, and sequence complete messages are 
displayed on the transcript window.

    The following figure shows the AXI read and write transactions and the corresponding SDRAM transactions.

    Figure 5. AXI Read and Write Transactions