I/O Lane

An I/O Lane contains: Twelve I/Os, a Lane Controller, I/O Gearing Logic, and a set of High-speed & 
Low-skew clock resources. The I/O Gearing Logic in a lane enables easy data transfer between the high-speed I/O pad and the Lower-speed FPGA core. The logic is used to either gear up the data rate from the FPGA Fabric to the memory device or gear down the data rate from the memory device to the FPGA fabric. For information about non-memory interface usage, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.

The Lane Controller contains the logic for managing the Read and Write signals and provides the Lane Clocks. Each Output Data (D) lane (x9) uses one I/O lane with 12 I/O pads each: Nine of the I/O pads are used for the Data (D) bits, and one for BWSx_N and the remaining I/O pads are left as spare.

Each Input Data (Q) lane(x9) uses one I/O lane with 12 I/O pads each-Nine of the I/O pads are used for the Data (D) bits and the remaining I/O pads are left as spare.

Address, Clock and Read/Write command (RPS_N and WPS_N) uses 3 I/O lanes.

Note: Depending on the configuration of the QDR memory, few of the I/Os in Address/Command Lanes are used. Some I/Os in these Lanes can be reused as normal I/Os. For Data Lanes, all 12 I/Os in the Lane are used.