DFI Interface

The DDR memory controller interface solution leverages the DDR PHY interface (DFI 3.1) for connections between the controller and the PHY. The control signal, write data, read data update, status, and training interfaces are listed in the following tables. Use the PolarFire FPGA DDR3 PHY configurator to expose the DFI interface. For more information about the interface, see to the DFI 3.1 Specification available on the DFI Group DDR PHY website.

Table 1. DFI Control Signal Interface (synchronous to SYS_CLK)
Signal Name Direction Description
DFI_ADDRESS_P0[15:0] Input DFI Address bus
DFI_ADDRESS_P1[15:0] Input DFI Address bus
DFI_ADDRESS_P2[15:0] Input DFI Address bus
DFI_ADDRESS_P3[15:0] Input DFI Address bus
DFI_BANK_P0[2:0] Input DFI bank bus (only for DDR3 and DDR4)
DFI_BANK_P1[2:0] Input DFI bank bus (only for DDR3 and DDR4)
DFI_BANK_P2[2:0] Input DFI bank bus (only for DDR3 and DDR4)
DFI_BANK_P3[2:0] Input DFI bank bus (only for DDR3 and DDR4)
DFI_CAS_N_P0 Input DFI column address strobe (only for DDR3 and DDR4)
DFI_CAS_N_P1 Input DFI column address strobe (only for DDR3 and DDR4)
DFI_CAS_N_P2 Input DFI column address strobe (only for DDR3 and DDR4)
DFI_CAS_N_P3 Input DFI column address strobe (only for DDR3 and DDR4)
DFI_CKE_P0[0] Input DFI clock enable
DFI_CKE_P1[0] Input DFI clock enable
DFI_CKE_P2[0] Input DFI clock enable
DFI_CKE_P3[0] Input DFI clock enable
DFI_CS_N_P0[0] Input DFI chip select
DFI_CS_N_P1[0] Input DFI chip select
DFI_CS_N_P2[0] Input DFI chip select
DFI_CS_N_P3[0] Input DFI chip select
DFI_ODT_P0[0] Input DFI on-die termination control
DFI_ODT_P1[0] Input DFI on-die termination control
DFI_ODT_P2[0] Input DFI on-die termination control
DFI_ODT_P3[0] Input DFI on-die termination control
DFI_RAS_N_P0 Input DFI row address strobe (only for DDR3 and DDR4)
DFI_RAS_N_P1 Input DFI row address strobe (only for DDR3 and DDR4)
DFI_RAS_N_P2 Input DFI row address strobe (only for DDR3 and DDR4)
DFI_RAS_N_P3 Input DFI row address strobe (only for DDR3 and DDR4)
DFI_RESET_N_P0 Input DFI reset
DFI_RESET_N_P1 Input DFI reset
DFI_RESET_N_P2 Input DFI reset
DFI_RESET_N_P3 Input DFI reset
DFI_WE_N_P0 Input DFI write enable (only for DDR3 and DDR4)
DFI_WE_N_P1 Input DFI write enable (only for DDR3 and DDR4)
DFI_WE_N_P2 Input DFI write enable (only for DDR3 and DDR4)
DFI_WE_N_P3 Input DFI write enable (only for DDR3 and DDR4)
Table 2. DFI Write Data Interface
Signal Name Direction Description
DFI_WRDATA_CS_N_P0[0] Input DFI write data chip select
DFI_WRDATA_CS_N_P1[0] Input DFI write data chip select
DFI_WRDATA_CS_N_P2[0] Input DFI write data chip select
DFI_WRDATA_CS_N_P3[0] Input DFI write data chip select
DFI_WRDATA_EN_P0[63:0]1 Input DFI write data and data mask enable
DFI_WRDATA_EN_P1[63:0] Input DFI write data and data mask enable
DFI_WRDATA_EN_P2[63:0] Input DFI write data and data mask enable
DFI_WRDATA_EN_P3[63:0] Input DFI write data and data mask enable
DFI_WRDATA_MASK_P0[15:0]1 Input DFI write data byte mask
DFI_WRDATA_MASK_P1[15:0]1 Input DFI write data byte mask
DFI_WRDATA_MASK_P2[15:0]1 Input DFI write data byte mask
DFI_WRDATA_MASK_P3[15:0]1 Input DFI write data byte mask
DFI_WRDATA_P0[127:0]1 Input These signals transfer write Data from memory controller to PHY
DFI_WRDATA_P1[127:0]1 Input These signals transfer write Data from memory controller to PHY
DFI_WRDATA_P2[127:0]1 Input These signals transfer write Data from memory controller to PHY
DFI_WRDATA_P3[127:0]1 Input These signals transfer write Data from memory controller to PHY
Note: Depends on DQ width (see Table 1 and Table 2).
Table 3. DFI Read Data Interface
Signal Name Direction Description
DFI_RDDATA_CS_N_P0[0] Input DFI read data chip select
DFI_RDDATA_CS_N_P1[0] Input DFI read data chip select
DFI_RDDATA_CS_N_P2[0] Input DFI read data chip select
DFI_RDDATA_CS_N_P3[0] Input DFI read data chip select
DFI_RDDATA_EN_P0[63:0]1 Input DFI read data enable
DFI_RDDATA_EN_P1[63:0]1 Input DFI read data enable
DFI_RDDATA_EN_P2[63:0]1 Input DFI read data enable
DFI_RDDATA_EN_P3[63:0]1 Input DFI read data enable
DFI_RDDATA_VALID_W0[7:0]1 Output DFI read data valid
DFI_RDDATA_VALID_W1[7:0]1 Output DFI read data valid
DFI_RDDATA_VALID_W2[7:0]1 Output DFI read data valid
DFI_RDDATA_VALID_W3[7:0]1 Output DFI read data valid
DFI_RDDATA_W0[127:0]1 Output DFI read data
DFI_RDDATA_W1[127:0]1 Output DFI read data
DFI_RDDATA_W2[127:0]1 Output DFI read data
DFI_RDDATA_W3[127:0]1 Output DFI read data
Note:
  1. 1.Depends on DQ width (see Table 1 and Table 2).
Table 4. DFI Write Calibration Interface
Signal Name Direction Description
CAL_L_BUSY Input Write Calibration Busy. Indicates this interface is not accepting new commands. A command is accepted when CAL_L_R_REQ or CAL_L_W_REQ is set and CAL_L_BUSY is low.
CAL_L_DATAOUT[511:0]1 Input Write calibration data output from the controller

Depends on DQ width.
CAL_L_D_REQ Input Write calibration data request from the controller.
CAL_L_R_VALID Input Write calibration read valid from the controller.
CAL_L_DATAIN[511:0]1 Output Write calibration data input to the controller

Depends on DQ width.
CAL_L_DM_IN[63:0]1 Output Write calibration data mask input to the controller

Depends on DQ width.
CAL_L_R_REQ Output Write calibration read request to the controller.
CAL_L_W_REQ Output Write calibration write request to the controller.
CAL_SELECT Output Write Calibration Select to the controller.
CAL_INIT_ACK2 Input Calibration initialization bus available handshake from DDR controller.
CAL_INIT_CS[1:0]2 Output Calibration initialization bus chip select.
CAL_INIT_MR_ADDR[7:0]2 Output Calibration initialization bus mode register write address.
CAL_INIT_MR_DATA[17:0]2 Output Calibration initialization bus mode register write data.
CAL_INIT_MR_MASK[17:0]2 Output Calibration initialization bus mode register write mask.
CAL_INIT_MR_W_REQ2 Output Calibration initialization bus mode register write request.
Notes:
  1. 1.Depends on DQ width (see Table 1 and Table 2).
  2. 2.These ports are only for DDR4.
  3. 3.The DRAM interface is same as Table 8 for DDR PHY only solution.
Table 5. DFI Training Interface
Signal Name Direction Description
DFI_RDLVL_CS_N[0] Input Chip select for read data eye training
DFI_RDLVL_EN Input PHY read data eye training enable
DFI_RDLVL_GATE_EN Input PHY read gate training enable
DFI_WRLVL_CS_N[0] Input Chip select for write leveling
DFI_WRLVL_EN Input PHY write leveling logic enable
DFI_WRLVL_STROBE Input Initiates capture of write level response
DFI_RDLVL_RESP[7:0] Output Indicates data eye or gate training complete
DFI_WRLVL_RESP[7:0] Output Indicates PHY has completed write leveling
Table 6. DFI Status Interface
Signal Name Direction Description
DFI_INIT_START Input DFI setup stabilization
DFI_INIT_COMPLETE Output PHY initialization complete
Table 7. DFI Clock and Miscellaneous
Signal Name Direction Description
PLL_LOCK Output PLL lock indicator
PLL_REF_CLK Input PLL reference clock
SYS_CLK Output PLL system clock output to controller
SYS_RESET_N Input Global reset input
SYNC_SYS_RST_N Output Synchronized reset output
CTRLR_READY_IN Input Controller ready status from controller to PHY
CTRLR_READY_OUT Output Controller ready status from PHY to controller
DFI_TRAINING_COMPLETE Output PHY output to controller to indicate training complete
Parent topic: DDR Subsystem Ports