Timing

Figure 1 shows a typical DDR3 protocol sequence and behavior of DFI and DRAM interfaces. All of the DDR protocol timing must be taken care by the controller. PHY is just an I/O and is responsible for timing parameters like setup time, hold time, clock duty cycle, and jitter. The PHY Timing Parameters are defined in the DFI 3.1 specification.

The following figure shows the continuous multi-burst operation on WRITE and READ, and also includes commands like PRECHARGE and REFRESH.

Figure 1. CONTINUOUS MULTI-BURST WRITE AND READ ON DFI/DRAM