The following are the guidelines for connecting the device to the DDR4 memory:
- DDR4 data nets have dynamic ODT built into the controller and SDRAM. The configurations are 80 Ω, 120 Ω, and 240 Ω. DQ lines do not need VTT termination. However, VTT termination resistors need to be placed at the end of address and control lines on the PCB.
- Characteristic impedance: Z0 is typically 50 Ω and Zdiff (differential) is 100 Ω.
The following figure shows the features supported by PolarFire FPGA in the DDR4 memory interface.
Figure 1. DDR4 Interface Example
