Training Logic

The training process is as follows:

  1. 1.CQP, Q delay controls are initialized with default values.
  2. 2.The test data patterns [0x96, 0x2d, 0x5a, 0xb4, 0x69, 0xd2, 0xa5, 0x4b] are written to Q.
  3. 3.The test data patterns are read at falling edges of CQP.
  4. 4.If all 8 test data patterns are read, the following conditions are verified for all data patterns:
    • If Q (data pattern) matches on falling edge of CQP. Q is moved to check the next data pattern.
    • If Q (data pattern) does not match, the training logic adjusts the IOD tap delay values as shown in Figure 2 and Figure 3.
    • If less than 8 patterns are matched, the training process is repeated from Step 2.
    • If Q_DELAY_LINE_OUT_OF_RANGE is asserted, TRAINING_ERROR and TRAINING_COMPLETE flags are asserted and then, the training process is repeated from Step 2.
  5. 5.Q is moved back to center of falling edge of CQP.
  6. 6.A sweep on CQP is performed to find the center of the rising edge data similar to step 3, 4 and 5. This covers all the Q bits per lane (9 bits per lane).
  7. 7.Step 2 is repeated for all lanes.
Note: Training is not shown on a per-Q basis, for brevity and clarity. CQN is generated in QDR IP.
Note: QDR training remains valid across PVT.

The timing relationships between CQP, CQN, data (Q), and data valid (before training begins) is shown in the following figure.

Figure 1. Data Capture before Training begins

At first, the falling edge data alignment is done concurrently with the data_valid alignment. As a result, the data_valid properly frames the 8-bit burst coming from the QDR device and the CQN centers the falling edge data (f0, f1, f2, f3).

Note: CQN is not moved because it cannot be moved in the specified architecture; instead, Q is moved to align with CQN by performing write and read of 8 different patterns and selecting a match if and only if all patterns match. This is done on a per-Q basis, with the exception of data framing, which is only performed on Q<0>.

A high-level timing diagram of alignment is shown in the following figure.

Figure 2. Data capture after aligning data valid and falling edge data to CQN

Next, CQP is aligned with the rising edge data by performing write and read of 8 different patterns and selecting a match if and only if all patterns match.

Figure 3. Data capture after moving CQP to center rising edge data

The process is then repeated for all Q bits (9 bits per lane) and for all lanes.