QDR SRAM Read

QDR SRAM Reads are requested by asserting the READ_N[x] signal low, and by driving the address on the RADDR. QDR controller asserts the RVALID to high when valid data is available on RDATA.

The following rules are applicable for the read requests in the user interface:

  1. 1.A Read is accepted by the Subsystem on any SYS_CLK clock cycle where the READ_N[x] signal is asserted to Low. Each Read Transaction performs the 2/4 burst Read Operations as per the QDR configuration.
  2. 2.Multiple Reads can be initiated by asserting the multiple READ_N[x] signals to Low. The address RADDR[SRAM_ADDR_WIDTH*(x+1) -1 : 0] and RDATA[SRAM_DATA_WIDTH*(x+1)*burst_mode - 1:0] will be the corresponding Read Address and Data for the Read Transaction associated with READ_N[x].
    • When QDR is configured for 2 Burst Mode, four burst Reads are initiated in single SYS_CLK clock cycle by using READ_N[3:0].
    • When QDR is configured for 4 Burst Mode, two burst Reads are initiated in single SYS_CLK clock cycle by using READ_N[1:0].
Figure 1. Read in 4 Burst Mode