Read Data Eye Training

After the fifth step, the controller initiates The READ Data Eye training in the following sequence.

  1. 1.The controller reads a continuous data pattern of ‘00’ followed by ‘FF’ from DRAM. This is same as enabling MPR and reading a fixed pattern from MPR for DDR3/4. DDR3 supports only one pattern in MPR.
  2. 2.Enabling the data flow for DDR3/4 from MPR is similar to what is done in DQS Gate training. For DDR3/4, the controller must set MR3 bit 2 to 1 (data flow from MPR) by issuing the MRS command.
  3. 3.The controller must assert DFI_RDLVL_EN = 1 to initiate READ DATA EYE training. The Training IP sweeps the input tap delay, reads the data and compares it with the expected results.
  4. 4.The left and right margins of the passing data are stored for all the bits in the byte lane. The left and right margins of each bit are analyzed and the appropriate delay value is applied to each bit to maximize the valid data window.
  5. 5.After the completion of READ Data eye training, the Training IP asserts DFI_RDLVL_RESP. After sampling DFI_RDLVL_RESP = 1, the controller can de-assert DFI_RDLVL_EN = 0. For DDR3/4, the controller must write 0 to MR3 bit 2 for restoring the normal data flow on the DQ bus.
Note: For DDR3/4, the controller must issue the regular ‘READ’ commands to read data from the MPR register. For LPDDR3, the controller must issue mode register read to MR32 or MR40.

The following figure shows READ DATA EYE before and after training.