Port List

The following table lists the QDR ports.

Table 1. QDR Signals and Descriptions
Name Width Direction Description
Generic Signals
SYS_CLK 1 Output Clock for User Logic generated by the embedded PLL. All User Interface signals are synchronous to this clock. Always on the global clock network.
RESET_N 1 Input Active-low asynchronous system reset.
PLL_REF_CLK   Input Reference clock to the PLL.
PLL_LOCK 1 Output Lock signal. This signal is generated by the PLL to indicate that the PLL is locked on to the PLL_REF_CLK signal.
TRAINING_COMPLETE 1 Output Indicates that Training is complete.

The user logic must check for TRAINING_COMPLETE = 1 and TRAINING_ERROR = 0 before accessing the QDR memory.

TRAINING_ERROR[2:0] 3 Output – Bit 0: Reserved

– Bits [2:1]

  • 0: No error.
  • 1: Timeout error, data VALID is received during Q training.
  • 2: No solution found during training.

If no solution is found, restart the Training process described in Training Logic.

User Interface Signals
READ_N 4 Input Read request with address specified on RADDR bus.
  • 4-bit Wide if Burst Size is 2.
  • 2-bit Wide if Burst Size is 4.
WRITE_N 4 Input Write request with address specified on WADDR bus.
  • 4-bit Wide if Burst Size is 2.
  • 2-bit Wide if Burst Size is 4.
WSTRB_N SRAM_DATA_WIDTH / 9 * 8 Input Write strobe for write transaction.
WADDR (QDR SRAM Address Width)*4 Input Write addresses for each beat.

Width is (QDR SRAM Address Width)*4 if burst size is 2, (QDR SRAM Address Width)*2 if burst size is 4

  • In Burst of 2: {ADDR3, ADDR2, ADDR1, ADDR0}
  • In Burst of 4: {ADDR1, ADDR0}
RADDR (QDR SRAM Address Width)*4 Input Read addresses for each beat.

Width is (QDR SRAM Address Width)*4 if burst size is 2, (QDR SRAM Address Width)*2 if burst size is 4

  • In Burst of 2: {ADDR3, ADDR2, ADDR1, ADDR0}
  • In Burst of 4: {ADDR1, ADDR0}
WDATA (QDR SRAM Data Width)*8 Input Write data
RDATA (QDR SRAM Data Width)*8 Output Read data, valid when RVALID is asserted
RVALID 1 Output Read data valid
QDR SRAM Interface
D[X:0] 9/18/36

(X=8,17, or 35)

Output Data Output Bus
WPS_N 1 Output Write port select - active-low
BWS0_N 1 Output Byte write select (BWS) 0 - active‐low
BWS1_N 1 Output Byte write select (BWS) 1 - active‐low
BWS2_N 1 Output Byte write select (BWS) 2 - active‐low
BWS3_N 1 Output Byte write select (BWS) 3 - active‐low
A[X:0] 18,19,20, or 21

(X=17,18,19, or 20)

Output Address inputs
Q[X:0] 9,18, or 36

(X=8,17, or 35)

Input Data input bus
RPS_N 1 Output Read port select - active‐low
QVALID 1 Input Valid output indicator. Not used in current QDR subsystem
KP 1 Output Positive Clock Output
KN 1 Output Negative Clock Output
CQP 1 Input Synchronous echo Clock input
DOFF_N 1 Output Initially, DOFF_N is 0. After calibration, DOFF_N is set to 1.

If Expose DOFF_N port option is selected in the configurator, the DOFF_N signal is exposed and taken care by the QDR controller.

If Expose DOFF_N port option is not selected in the configurator, the DOFF_N signal does not get exposed and must be taken care on the board using a pull-up resistor (check the memory model data sheet).