QDR SRAM Write

QDR SRAM Writes are requested by asserting the WRITE_N[x] signal low, and by driving the Address on the WADDR. The following rules are applicable for the write requests in the user interface:

  1. 1.A Write is accepted by the Subsystem on any SYS_CLK clock cycle, where the WRITE_N[x] signal is asserted to Low. Each Write Transaction performs the 2/4 Burst Write operations as per the QDR configuration.
  2. 2.Multiple Writes can be initiated by asserting the multiple WRITE_N[x] signals to low. The address WADDR[SRAM_ADDR_WIDTH*(x+1) -1: 0] and DATA[SRAM_DATA_WIDTH*(x+1)*burst_mode -1:0] will be the corresponding Write Address and Data for the Write Transaction associated with WRITE_N[x].
    • When QDR is configured for 2 Burst mode, four Burst Writes are initiated in single SYS_CLK clock cycle by using WRITE_N[3:0].
    • When QDR is configured for 4 Burst mode, two Burst Writes are initiated in single SYS_CLK clock cycle by using WRITE_N[1:0].
  3. 3.Maximum of 8 SRAM_DATA_WIDTH Bit writes to QDR SRAM are initiated in a single SYS_CLK clock cycle.
Figure 1. Write in 4 Burst Mode