Configuring the Fabric DDR Subsystem

The Fabric DDR subsystem macro (DDR3, DDR4, and LPDDR3) located in the Libero IP catalog must be instantiated in SmartDesign to access the DDR memory from the FPGA fabric through the subsystem. The DDR Configurator, shown in Figure 1, configures the DDR subsystem. It supports the following modes:

• Preset configuration—allows selection from a list of memory vendors and devices to preset all of the memory initialization and timing parameters into the DDR Configurator, as shown in Figure 1.
  Note: For DDR3, preset configuration is supported for 1333, 1600, 1866, and 2133 at 666.67 MHz (minimum tCK ≥ 1.5 ns). For DDR4, preset configuration is supported for 1600, 1866, 2133, 2400, 2666, 2933, and 3200 at 800 MHz (minimum tCK ≥ 1.25 ns).
  Figure 1. DDR3 Configurator—Preset Configuration

  
• User configuration—allows manual configuration of all memory initialization and timing parameters. This can be saved as a preset configuration, as shown in Figure 2.
  Note: See the DDR vendor datasheets before configuring DDR parameters.
  Figure 2. User-Defined Configuration

  

The following sections describe the configuration options available in the DDR Configurator.