RTL_FULL Simulation

The QDR subsystem is used to access QDR SRAMs directly, as shown in the following figure. User logic is connected directly to the QDR subsystem using the user interface.

Figure 1. QDR Subsystem accessed through User Interface

After successful QDR initialization, the User Interface Master initiates Read or Write to the QDR memory. The following steps describe how to create a design for accessing the QDR memory from the user interface master in the FPGA fabric:

  1. 1.Create a SmartDesign, and instantiate the QDR component.
  2. 2.Configure the QDR Subsystem as described in Implementation. In the following example, a design is created to access the QDR memory with 36-Bit Data Width, 19-Bit Address Width and Burst size of 4.
    Figure 2. QDR Configuration- RTL_FULL
  3. 3.Instantiate the User Interface Master logic in the SmartDesign canvas. Ensure that the User Interface Master logic accesses the QDR subsystem only after TRAINING_COMPLETE is high.
  4. 4.In the SmartDesign canvas, connect the blocks, as shown in the following figure.
    Figure 3. SmartDesign Connections
  5. 5.Create a new SmartDesign Testbench to simulate the design.
  6. 6.Instantiate the top-level design component and the QDR memory simulation model.
  7. 7.Configure CLK_GEN to generate the PLL reference clock and connect to PLL_REF_CLK.
  8. 8.Connect the blocks in SmartDesign Testbench, as shown in the following figure.
    Figure 4. QDR SmartDesign Testbench
  9. 9.On Libero Design Flow -> Verify Pre-synthesized Design, select Simulate.
  10. 10.The QDR subsystem performs the training and asserts the TRAINING_COMPLTETE. The following figure shows the User interface read and writes transactions and the corresponding QDR SRAM transactions.
    Figure 5. QDR Read and Write Transactions- RTL_FULL