The DDR controller can be configured with multi-burst capability if the native-interface mode is selected in the DDR Configurator. This feature extends the allowable range of requests at the burst size (L_B_SIZE) port to accommodate requests larger than the programmed burst length. It also handles requests with starting addresses not aligned to a burst boundary, breaking them up as necessary to prevent wrapped or non-sequential data access that may otherwise occur. For more information, see Data Ordering with Non-Aligned Starting Addresses.
The following figure shows a sample write sequence with the multi-burst
capability enabled. In this sequence, a write request is issued with a starting address
(L_ADDR) 0x08 and a request size (L_B_SIZE) of 32 bytes.
Figure 1. Sample Write Sequence Demonstrating Multi-Burst Operation
The following points summarize a write sequence with multi-burst capability:
- 1.The L_W_REQ signal is first asserted along with the L_ADDR signal, and the L_B_SIZE
signal is set to 32.
- 2.The L_W_REQ signal is deasserted, indicating no other write requests are required.
- 3.As a result of the write request, the subsystem asserts the row address (A), bank
address (BA), and chip select (CS_N) using the activate command to open the bank at the
requested row.
- 4.The subsystem issues the write command with a column address corresponding to the
request.
- 5.The subsystem issues the next write command with the corresponding column address.
- 6.The written data begins to appear on the SDRAM bus on the DQ lines.
- 7.L_W_VALID is asserted, and written data appears on the native interface, and then
L_W_VALID is deasserted.
The following figure shows a sample read sequence with the multi-burst capability enabled. In this example, a read request is issued with a starting address (L_ADDR) 0x08 and a request size (L_B_SIZE) of 32 bytes.
Figure 2. Sample Read Sequence Demonstrating Multi-Burst Operation
The following points summarize a read sequence with multi-burst capability:
- 1.The L_R_REQ signal is first asserted along with the L_ADDR signal, and the L_B_SIZE
signal is set to 32.
- 2.The L_R_REQ signal is deasserted, indicating no other read requests are required.
- 3.As a result of the read request, the subsystem asserts the row address (A), bank
address (BA), and chip select (CS_N) using the activate command to open the bank at the
requested row.
- 4.The subsystem issues the read command with a column address corresponding to the
request.
- 5.The subsystem issues the next read command with the corresponding column address.
- 6.The read data begins to appear on the SDRAM bus on the DQ lines.
- 7.L_R_VALID is asserted, and read data appears on the native interface, and then
L_R_VALID is deasserted.