Clocking Structure

The QDR subsystem require a dedicated PLL to generate the clocks, which are then distributed throughout the subsystem using HS_IO_CLK routes, dedicated pads, and fabric clock routing. This PLL generates aligned clocks for all sub-blocks for smooth operation and synchronous communication with the user logic. The PLL generates three required clocks-HS_IO_CLK, HS_IO_CLK phase shifted by 90° (HS_IO_CLK_90), and controller clock (SYS_CLK). The two HSIO clocks (HS_IO_CLK and HS_IO_CLK_90) are routed to the PHY using HS_IO_CLK routing resources (for low skew) and multiplexers. These two clocks generate the QDR SRAM interface signals. SYS_CLK is routed to the QDR controller and user logic in the fabric. The QDR Memory Clock to SYS_CLK ratio is 4:1.

The PLL generates the QDR memory clocks (KP and KN) as shown in the following figure.

Figure 1. QDR Clocking Structure

The dedicated Clock Input Pad (CCC_xx_CLKIN_N_m) and Output Pad (CCC_xx_PLLy_OUTz) is selected depending on the QDR subsystem placement constraint (where xx = SE/NE/NW/SW, y = 0/1, z = 0/1 and m=0/1/2/3).

Note: Timing constraints are not required for output signals (Address, Command and Data). Because, these output signals are shifted 90° from the K clock.