SDRAM reads are requested in the native interface by asserting the L_R_REQ signal, and by driving the starting address and burst size on the L_ADDR and L_B_SIZE signals respectively. The L_AUTO_PCH signal may also be asserted along with the L_R_REQ signal to issue the read as a read with auto-precharge. A read can be requested with auto-precharge by asserting the L_AUTO_PCH signal along with the L_R_REQ signal.
The following are the rules for read requests at in the native interface:
- A read is accepted by the subsystem on any clock cycle where the L_R_REQ signal is asserted while the L_BUSY signal is deasserted. After L_BUSY is deasserted by the subsystem, the L_R_REQ signal may remain asserted to request a follow-on read transaction. The L_R_REQ signal may remain asserted over any number of clock periods to generate any number of cascaded read requests.
- The values of the L_ADDRL_B_SIZE, and L_AUTO_PCH signals are captured when the L_BUSY signal is low. The L_B_SIZE and L_AUTO_PCH signals can be tied to fixed values, if desired.
- The L_R_REQ signal cannot be asserted while the L_W_REQ signal is asserted.
- The read data valid (L_R_VALID) signal is asserted when valid data is available at the L_DATAOUT bus.
- The timing relationship between an initial L_R_REQ, L_R_VALID, and L_BUSY or between L_BUSY assertions and de-assertions as a result of multiple cascaded reads varies depending on the status of the banks being accessed, configuration port settings, refresh status, and initialization status.
- The user logic must not rely on any fixed timing relationship between the L_R_REQ, L_R_VALID, and L_BUSY signals.