The integrated PHY, which consists of the I/O lane and the training logic, provides a physical interface to DDR3, DDR4, and LPDDR3 SDRAM devices. It receives commands from the DDR controller and generates the DDR memory signals required to access the external DDR memory. The training logic in the PHY manages DFI 3.1 training requests between the I/O lane and the DDR controller. For more information about the DDR PHY-only integration, see DDR PHY-Only Solution Integration. For more information about Octal DDR PHY-Only Solution, see Octal DDR PHY-Only Solution.
Figure 1. DDR PHY
