Contents

Introduction 1. Acronyms 2. MSS DDR Memory Controller 2.1. Training Logic for Embedded DDR Controller 3. Fabric DDR Subsystem 3.1. Features 3.2. Performance 3.3. Resource Utilization 3.4. Functional Description 3.4.1. DDR Controller 3.4.1.1. Periodic Functions 3.4.1.1.1. Refresh 3.4.1.1.2. ZQ Calibration 3.4.1.2. Look-Ahead Operations (Precharge and Auto-Precharge) 3.4.1.3. Bank Management 3.4.1.4. Multi-Burst Capability (Native-Interface Mode Only) 3.4.1.5. Data Ordering with Non-Aligned Starting Addresses 3.4.1.6. Auto-Precharge 3.4.1.7. ECC 3.4.2. Clocking Structure 3.4.3. Integrated PHY 3.4.3.1. I/O Lane 3.4.3.2. Training Logic for Fabric DDR Controller 3.5. DDR Subsystem Ports 3.5.1. DDR PHY-Only Solution Ports 3.5.2. DFI Interface 3.6. Functional Timing Diagrams 3.6.1. Native Interface Transactions 3.6.1.1. SDRAM Writes 3.6.1.1.1. Sample Write Sequence 3.6.1.2. SDRAM Reads 3.6.1.2.1. Sample Read Sequence 3.6.2. AXI Transactions 3.7. DDR PHY-Only Solution Integration 3.7.1. Controller and PHY Integration 3.7.2. PHY Configurator 3.7.3. Initialization and Bring-Up of the DDR Subsystem 3.7.3.1. DFI Initialization 3.7.3.2. DRAM Initialization 3.7.3.3. ZQ Calibration 3.7.3.4. Write Leveling 3.7.3.5. DQS Gate Training 3.7.3.6. Read Data Eye Training 3.7.3.7. Write Calibration 3.7.3.8. Simple Burst Write 3.7.3.9. Simple Burst Read 3.7.4. Timing 3.8. Octal DDR PHY-Only Solution 3.8.1. Configurator 3.8.2. Timing Constraints 3.8.3. Place and Route Pin-Out Rules 3.9. Implementation 3.9.1. Selecting the Memory Device 3.9.1.1. DDR4 Optimization Guidelines 3.9.2. Configuring the DDR3 Subsystem 3.9.3. Configuring the LPDDR3 Subsystem 3.9.4. Configuring the DDR4 Subsystem 3.9.5. Simulating the DDR Subsystem 3.9.6. Design Constraints 3.9.6.1. Timing Constraints 3.9.6.2. Physical Constraints 3.9.6.2.1. Using PDC 3.9.6.2.2. Using I/O Editor 3.10. Functional Examples 3.10.1. Accessing DDR Subsystem Through AXI4 Interface 3.10.2. Accessing DDR Subsystem Through Native Interface 3.10.3. Accessing DDR Memory Using a Third-Party DDR Controller and the DDR PHY-Only Solution 4. Initialization Sequence 4.1. DDR3 4.2. DDR4 4.3. LPDDR3 4.4. LPDDR4 (For PolarFire SoC FPGA Only) 5. Training Logic 6. QDR Memory Controller 6.1. Features 6.2. Performance 6.2.1. Read Latency 6.3. Functional Description 6.3.1. QDR Controller 6.3.1.1. Integrated PHY 6.3.1.1.1. I/O Lane 6.3.1.2. Training Logic 6.3.2. Clocking Structure 6.3.3. Port List 6.4. Functional Timing Diagrams 6.4.1. Write Strobe Mapping 6.4.1.1. Burst of 2 6.4.1.2. Burst of 4 6.4.2. QDR SRAM Write 6.4.3. QDR SRAM Read 6.5. Implementation 6.5.1. Configuring QDR Memory Controller IP 6.5.1.1. Pipelining Latency 6.5.2. Simulating QDR Memory Controller 6.5.3. Design Constraints 6.5.3.1. Timing Constraints 6.5.3.2. Physical Constraints 6.5.4. QDR Resource Utilization 6.6. Functional Example 6.6.1. RTL_FULL Simulation 6.6.2. BFM Simulation 6.6.3. RTL_Fast Simulation 6.7. PCB Recommendations 7. PolarFire Board Design Recommendations 7.1. DDR3 7.1.1. DDR3 Layout Guidelines 7.1.1.1. DDR3 Routing Topology 7.1.1.2. Skew Constraints For Signal Groups 7.2. LPDDR3 7.2.1. LPDDR3 Layout Guidelines 7.2.1.1. LPDDR3 Routing Topology 7.2.1.2. Skew Matching Constraints 7.3. DDR4 7.3.1. DDR4 Layout Guidelines 7.3.1.1. DDR4 Routing Topology 7.3.1.2. Skew matching constraints 8. PolarFire SoC Board Design Recommendations 8.1. DDR3 8.1.1. DDR3 Layout Guidelines 8.1.1.1. DDR3 Routing Topology 8.1.1.2. Skew Constraints for Signal Groups 8.2. LPDDR3 8.2.1. LPDDR3 Layout Guidelines 8.2.1.1. LPDDR3 Routing Topology 8.2.1.2. Skew Matching Constraints 8.3. DDR4 8.3.1. DDR4 Layout Guidelines 8.3.2. DDR4 Routing Topology 8.3.2.1. Skew Matching Constraints 8.4. LPDDR4 8.4.1. LPDDR4 Layout Guidelines 8.4.2. LPDDR4 Routing Topology 8.4.2.1. Single-channel LPDDR4 Interface Routing 8.4.2.2. Dual-Channel LPDDR4 Interface Routing 8.4.2.3. Routing Recommendation 8.4.2.4. Skew Machine Constraints 8.4.3. Designing LPDDR4 Interface with Polarfire SoC FPGA 9. Debugging Techniques 9.1. Debug Tools 9.1.1. SmartDebug 9.1.2. Identify RTL Debugger 9.1.3. Hardware Probes 9.2. Design Debug During Simulation 9.3. Hardware Debug 10. Appendix: Supported Memory Configurations 11. Appendix: Timing Parameters 12. Appendix: Fabric DDR Placement Locations 13. Revision History 14. Microchip FPGA Support 15. Microchip Information The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service