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Libero SoC Design Suite Help Documentation v2024.1
1 What's New
Information about what is new in Libero SoC Design Suite
1.1 What's New in Libero SoC Design Suite v2024.1
1.2 What's New In MSS Configurator v2024.1
1.3 What's New In SmartHLS Compiler v2024.1
2 Download Help
Information to help you download the Libero SoC Design Suite documentation
2.1 Latest Release
View/Download the latest Libero SoC Design Suite documentation
2.2 Previous Releases (PDF Version)
View/Download the archive Libero SoC Design Suite documentation in PDF format
3 SmartHLS Compiler
Information about SmartHLS Compiler
3.1 Overview
Welcome to the User Manual of SmartHLS.
3.2 Getting Started
Information and resources to help you get started using SmartHLS as quickly as possible.
3.3 Technical Support
3.4 Quick Start Tutorial
Learn how to use some of the major features and optimization techniques of SmartHLS.
3.5 Working with SmartHLS
Information and resources to help you work with SmartHLS.
3.6 Additional References
Information about the additional references to help you use SmartHLS.
3.7 SmartHLS™ Examples
Information about SmartHLS examples.
4 Installation and Licensing
Information about Libero SoC software installation and licensing
4 Introduction
4.1 Overview
4.2 System Requirements
4.3 Ordering and Downloading a License
4.4 Installing Libero SoC Design Suite
4.5 Using Libero SoC Design Suite in a Secure Environment
4.6 Troubleshooting Linux Installations
5 Design Flow
Information about Design Flow
5 Introduction
5.1 Overview
5.2 Managing Licenses
5.3 Getting Started
5.4 Creating and Verifying Designs
5.5 Libero SoC Constraint Management
5.6 Implementing Designs
5.7 Configure Hardware
5.8 Program Design
5.9 Debug Design
5.10 Handoff Design for Production
5.11 Handoff Design for Firmware Development (SmartFusion 2 and IGLOO 2)
5.12 Handoff Design for Debugging
5.13 References
6 Block Flow
Information about Block Flow
6 Introduction
6.1 Overview
6.2 Creating Blocks, Options, and Settings
6.3 Publishing Blocks
6.4 Guidelines for Creating Blocks
6.5 Instantiating Blocks in the Top-Level Design
6.6 Hierarchical Structure Resolution in Top-Level Projects
6.7 Synthesis
6.8 Resolving Place and Route Conflicts
6.9 Block PDC Commands
7 SmartDesign
Information about SmartDesign
7 Introduction
7.1 Understanding the SmartDesign Canvas
7.2 Creating a Synthesizable SmartDesign
7.3 Instantiating User HDL Modules, IP Cores, and Components in SmartDesign
7.4 Creating Pins and Ports for Connecting Instances in the SmartDesign
7.5 Connecting Instances in your SmartDesign
7.6 Finding Objects in Your Project
7.7 Using the Smart Search and Connect Tool
7.8 Working with Hierarchical SmartDesigns
7.9 Validating the SmartDesign Using the DRC
7.10 Managing Synthesis Attributes
7.11 Generating the SmartDesign Component
7.12 Creating a SmartDesign Testbench
7.13 Viewing the Design Memory Map
7.14 Exporting Memory Map Report
7.15 Exporting Interrupt Map Report
7.16 Appendix A - Glossary
7.17 Appendix B - Available Cores in Libero SoC Catalog
7.18 Appendix C - Keyboard Shortcuts
7.19 Appendix D – Component Types
7.20 Appendix E – Operations Native to SmartDesign
8 Netlist Viewer
Information about Netlist Viewer
8.1 Netlist Viewer
Information about Netlist Viewer
8.2 Netlist Viewer Interface
Information about Netlist Viewer Interface
9 I/O Editor
Information about I/O Editor
9 Introduction
9.1 Invoking the I/O Editor
9.2 Port View
9.3 Pin View
9.4 Package View
9.5 Interface—Specific I/Os and Views
9.6 Memory Interface View
9.7 XCVR View
9.8 IOD View
9.9 Floorplanner View
9.10 Other I/O Editor Windows
9.11 Export Physical Constraints (PDC)
9.12 Appendix
10 PDC Commands
Information about PDC commands for all families
10.1 PDC Commands for PolarFire
Information about PDC commands for PolarFire
10.2 PDC Commands for SmartFusion2 and IGLOO2
Information about PDC commands for SmartFusion2 and IGLOO2
11 Chip Planner
Information about Chip Planner
11 Introduction
11.1 About Chip Planner
11.2 Chip Planner Views
11.3 Display Options Window
11.4 Floorplanner View Window
11.5 Other Chip Planner Windows
11.6 Floorplanning Using Chip Planner
11.7 Netlist Views
11.8 Cross-Probing from SmartTime to Chip View/Netlist View
11.9 A - Limitations
12 Timing Constraints Editor
Information about Timing Constraints Editor
12 Introduction
12.1 About the Timing Constraints Editor
12.2 Required Constraints
12.3 Timing Exceptions
12.4 Adjusting Clock Information
12.5 Advanced Constraints
13 SmartTime Static Timing Analyzer
Information about SmartTime Static Timing Analyzer
13 Introduction
13.1 About SmartTime
13.2 Design Flows with SmartTime
13.3 Starting and Closing SmartTime
13.4 Configuring SmartTime Settings
13.5 SmartTime Toolbar
13.6 SmartTime Timing Analyzer
13.7 Advanced Timing Analysis
13.8 Generating Timing Reports
13.9 Timing Concepts
13.10 SmartTime Tutorials
13.11 SmartTime Dialog Boxes
13.12 Tcl Commands
13.13 Glossary
14 SmartPower
Information about SmartPower
14 Introduction
14.1 Starting SmartPower
14.2 SmartPower Interface
14.3 Power Options
Allows you to set options that affect graphical and textual reports.
14.4 Calculating Power
15 Programming and Debugging
Information about Programming and Debugging
15.1 FlashPro Express
Information about FlashPro Express
15.2 Secure Production Programming Solution (SPPS)
Information about Secure Production Programming Solution (SPPS)
15.3 SmartDebug
Information about SmartDebug
15.4 Job Manager
Information about Job Manager
16 Macro Library
Information about Macro Library for SmartFusion2, IGLOO2 and PolarFire
16.1 PolarFire Macro Library
Information about Macro Library for PolarFire
16.2 SmartFusion2 and IGLOO2 Macro Library
Information about Macro Library for SmartFusion2 and IGLOO2
16.3 RTG4 Macro Library
Information about Macro Library for RTG4
17 Custom Flow
Information about Custom Flow
17.1 PolarFire Custom Flow
Information about PolarFire Custom Flow
17.2 SmartFusion 2, IGLOO 2, and RTG4 Custom Flow
Information about SmartFusion 2, IGLOO 2, and RTG4 Custom Flow
18 Design Separation Methodology
Information about Design Separation Methodology
18 Introduction
18.1 Design Methodology
18.2 Example
19 Microchip Separation Verification Tool
Information about Microchip Separation Verification Tool
19 Introduction
19.1 Overview
19.2 Creating a Design
19.3 Extracting MSVT Files
19.4 Using the MSVT Tool
19.5 Report Conclusion
19.6 Reference Documents
20 PolarFire SoC Microcontroller Subsystem (MSS)
Information about PolarFire SoC Microcontroller Subsystem (MSS)
20.1 PolarFire SoC MSS Simulation
Information about PolarFire SoC MSS Simulation
20.2 PolarFire SoC MSS Configurator
Information about PolarFire SoC MSS Configurator
21 Tcl Command Reference
Information about Tcl Command Reference
21 Introduction
21.1 Tcl Scripting Overview
21.2 Building a Libero Design Using Tcl
21.3 Project Manager Tcl Commands
21.4 SmartDesign Tcl Commands
21.5 HDL Tcl Commands
21.6 Command Tools
21.7 MSS Tcl Commands
21.8 SmartTime Tcl Commands
21.9 SmartPower Tcl Commands
21.10 Programming and Configuration Tcl Commands
21.11 FlashPro Express Tcl Commands
21.12 Configure JTAG Chain Tcl Commands
21.13 SmartDebug Tcl Commands
21.14 System Builder Tcl Commands
21.15 Simultaneous Switching Noise Analyzer (SSNA) Tcl Commands
21.16 HSM Tcl Commands
21.17 Derive Constraints Tcl Commands
22 More Information
Additional information about other Microchip products
22.1 SmartHLS Compiler
22.2 FPGA Documentation
22.3 FPGA Kits and Hardware
22.4 SoftConsole
22.5 IP Cores
22.6 Mi-V RISC-V Soft CPUs
22.7 SynplifyPro
22.8 ModelSim ME
23 Technical Support
24 About Microchip
More information about Microchip
24 Microchip FPGA Support
24 Microchip Information