8.1 Power Architecture
The ATWILC3000A uses an innovative power architecture to eliminate the requirement for external regulators and reduce the number of off-chip components. This architecture is shown in the following figure. The Power Management Unit (PMU) has a DC/DC converter that converts VBAT to the core supply used by the digital and RF/AMS blocks. The typical values for the digital and RF/AMS core voltages are shown in the following table. The PA and eFuse are supplied by dedicated LDOs, and the VCO is supplied by a separate LDO structure.
Parameter | Typical |
---|---|
RF/AMS Core Voltage (VREG_BUCK) | 1.3V |
Digital Core Voltage (VDDC) | 1.1V |
The power connections shown provide a conceptual framework for understanding the ATWILC3000A power architecture. Refer to the reference design for an example of power supply connections, including proper isolation of the supplies used by the digital and RF/AMS blocks.