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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Introduction
Features
Reference Document
1 Configuration Summary
2 Block Diagram
3 Signal Description
4 Microchip Recommended Power Management Solutions
4.1 MCP16502 PMIC
4.2 MCP16501 PMIC
5 Safety and Security Features
5.1 Design for Safety and IEC60730 Class B Certification
5.2 Design for Security
5.3 Safety and IEC 60730 Features
5.4 Security Features
6 Package and Pinout
6.1 Packages
6.2 Pinout
7 Memories
7.1 Embedded Memories
7.2 External Memory
8 System Controller
8.1 Power-On Reset
9 Peripherals
9.1 Peripheral Mapping
9.2 Peripheral Identifiers
9.3 FLEXCOM Features
9.4 Peripheral Signal Multiplexing on I/O Lines
10 ARM926EJ-S Processor
11 Debug and Test
11.1 Description
11.2 Embedded Characteristics
11.3 Block Diagram
11.4 Application Examples
11.5 Debug and Test Pin Description
11.6 Functional Description
12 Boot Strategies
12.1 Standard Boot Strategy
12.2 Secure Boot Strategy
13 System Controller Write Protection (SYSCWP)
13.1 Functional Description
13.2 Register Summary
14 General Purpose Backup Registers (GPBR)
14.1 Description
14.2 Embedded Characteristics
14.3 Register Summary
15 Watchdog Timer (WDT)
15.1 Description
15.2 Embedded Characteristics
15.3 Block Diagram
15.4 Functional Description
15.5 Register Summary
16 Reset Controller (RSTC)
16.1 Description
16.2 Embedded Characteristics
16.3 Block Diagram
16.4 Functional Description
16.5 Register Summary
17 Real-Time Timer (RTT)
17.1 Description
17.2 Embedded Characteristics
17.3 Block Diagram
17.4 Functional Description
17.5 Register Summary
18 Real-Time Clock (RTC)
18.1 Description
18.2 Embedded Characteristics
18.3 Block Diagram
18.4 Product Dependencies
18.5 Functional Description
18.6 Register Summary
19 Shutdown Controller (SHDWC)
19.1 Description
19.2 Embedded Characteristics
19.3 Block Diagram
19.4 I/O Lines Description
19.5 Product Dependencies
19.6 Functional Description
19.7 Register Summary
20 Periodic Interval Timer (PIT)
20.1 Description
20.2 Embedded Characteristics
20.3 Block Diagram
20.4 Functional Description
20.5 Register Summary
21 64-bit Periodic Interval Timer (PIT64B)
21.1 Description
21.2 Embedded Characteristics
21.3 Block Diagram
21.4 Product Dependencies
21.5 Functional Description
21.6 Register Summary
22 Debug Unit (DBGU)
22.1 Description
22.2 Embedded Characteristics
22.3 Block Diagram
22.4 Product Dependencies
22.5 Functional Description
22.6 Register Summary
23 OTP Memory Controller (OTPC)
23.1 Description
23.2 Embedded Characteristics
23.3 Block Diagram
23.4 Product Dependencies
23.5 Functional Description
23.6 Register Summary
24 Special Function Registers (SFR)
24.1 Description
24.2 Embedded Characteristics
24.3 Register Summary
25 Bus Matrix (MATRIX)
25.1 Description
25.2 Embedded Characteristics
25.3 Memory Mapping
25.4 Special Bus Granting Techniques
25.5 No Default Host
25.6 Last Access Host
25.7 Fixed Default Host
25.8 Arbitration
25.9 Register Write Protection
25.10 Register Summary
26 Advanced Interrupt Controller (AIC)
26.1 Description
26.2 Embedded Characteristics
26.3 Block Diagram
26.4 Application Block Diagram
26.5 Detailed Block Diagram
26.6 I/O Line Description
26.7 Product Dependencies
26.8 Functional Description
26.9 Register Summary
27 Slow Clock Controller (SCKC)
27.1 Description
27.2 Embedded Characteristics
27.3 Block Diagram
27.4 Functional Description
27.5 Register Summary
28 Clock Generator
28.1 Description
28.2 Embedded Characteristics
28.3 Block Diagram
28.4 Slow Clock
28.5 Main Clock
28.6 PLL Controls
29 Power Management Controller (PMC)
29.1 Description
29.2 Embedded Characteristics
29.3 Block Diagram
29.4 Processor Clock Controller
29.5 USB Clock Controller
29.6 Free-Running Processor Clock
29.7 Peripheral and Generic Clock Controller
29.8 Programmable Clock Output Controller
29.9 Ultra-Low Power Mode and Fast Start-Up
29.10 Main Crystal Oscillator Failure Detection
29.11 32.768 kHz Crystal Oscillator Frequency Monitor
29.12 MCK Frequency Monitor
29.13 Recommended Programming Sequence
29.14 Clock Switching Details
29.15 Register Write Protection
29.16 Register Summary
30 Parallel Input/Output Controller (PIO)
30.1 Description
30.2 Embedded Characteristics
30.3 Block Diagram
30.4 Product Dependencies
30.5 Functional Description
30.6 Register Summary
31 External Bus Interface (EBI)
31.1 Description
31.2 Embedded Characteristics
31.3 EBI Block Diagram
31.4 I/O Lines Description
31.5 Application Examples
32 DDR-SDRAM Controller (MPDDRC)
32.1 Description
32.2 Embedded Characteristics
32.3 Block Diagram
32.4 Product Dependencies, Initialization Sequence
32.5 Functional Description
32.6 Software Interface/SDRAM Organization, Address Mapping
32 Register Summary
33 SDRAM Controller (SDRAMC)
33.1 Description
33.2 Embedded Characteristics
33.3 Signal Description
33.4 Software Interface/SDRAM Organization, Address Mapping
33.5 Product Dependencies
33.6 Functional Description
33.7 Register Summary
34 Static Memory Controller (SMC)
34.1 Description
34.2 Embedded Characteristics
34.3 I/O Lines Description
34.4 Interrupt Source
34.5 Multiplexed Signals
34.6 Application Example
34.7 Product Dependencies
34.8 External Memory Mapping
34.9 Connection to External Devices
34.10 Standard Read and Write Protocols
34.11 Automatic Wait States
34.12 Data Float Wait States
34.13 External Wait
34.14 Slow Clock Mode
34.15 Asynchronous Page Mode
34.16 Register Write Protection
34.17 Security and Safety Analysis and Reports
34.18 Scrambling/Unscrambling Function
34.19 Clearing Scrambling Keys on a Tamper Event
34.20 Register Summary
35 Programmable Multibit Error Correction Code Controller (PMECC)
35.1 Description
35.2 Embedded Characteristics
35.3 Block Diagram
35.4 Functional Description
35.5 Software Implementation
35.6 Register Summary
36 Programmable Multibit ECC Error Location Controller (PMERRLOC)
36.1 Description
36.2 Embedded Characteristics
36.3 Block Diagram
36.4 Functional Description
36.5 Register Summary
37 DMA Controller (XDMAC)
37.1 Description
37.2 Embedded Characteristics
37.3 Block Diagram
37.4 DMA Controller Peripheral Connections
37.5 Functional Description
37.6 Linked List Descriptor Operation
37.7 XDMAC Maintenance Software Operations
37.8 XDMAC Software Requirements
37.9 Register Summary
38 LCD Controller (LCDC)
38.1 Description
38.2 Embedded Characteristics
38.3 Block Diagram
38.4 I/O Lines Description
38.5 Product Dependencies
38.6 Functional Description
38.7 Register Summary
39 2D Graphics Engine (GFX2D)
39.1 Description
39.2 Embedded Characteristics
39.3 Block Diagram
39.4 Functional Description
39.5 Register Summary
40 Ethernet MAC 10/100 (EMAC)
40.1 Description
40.2 Embedded Characteristics
40.3 Block Diagram
40.4 Functional Description
40.5 Programming Interface
40.6 Register Summary
41 USB Device High Speed Port (UDPHS)
41.1 Description
41.2 Embedded Characteristics
41.3 Block Diagram
41.4 Typical Connection
41.5 Product Dependencies
41.6 Functional Description
41 Register Summary
42 USB Host High Speed Port (UHPHS)
42.1 Description
42.2 Embedded Characteristics
42.3 Block Diagram
42.4 Typical Connection
42.5 Product Dependencies
42.6 Functional Description
42 Register Summary
43 Audio Class D Amplifier (CLASSD)
43.1 Description
43.2 Embedded Characteristics
43.3 Block Diagram
43.4 Pin Name List
43.5 Product Dependencies
43.6 Functional Description
43.7 Register Summary
44 Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.1 Description
44.2 Embedded Characteristics
44.3 Block Diagram
44.4 I/O Lines Description
44.5 Product Dependencies
44.6 Functional Description
44.7 Register Summary
45 Synchronous Serial Controller (SSC)
45.1 Description
45.2 Embedded Characteristics
45.3 Block Diagram
45.4 Application Block Diagram
45.5 SSC Application Examples
45.6 Pin Name List
45.7 Product Dependencies
45.8 Functional Description
45.9 Register Summary
46 Flexible Serial Communication Controller (FLEXCOM)
46.1 Description
46.2 Embedded Characteristics
46.3 Block Diagram
46.4 I/O Lines Description
46.5 Product Dependencies
46.6 Register Accesses
46.7 USART Functional Description
46.8 SPI Functional Description
46.9 TWI Functional Description
46.10 Register Summary
47 Quad Serial Peripheral Interface (QSPI)
47.1 Description
47.2 Embedded Characteristics
47.3 Block Diagram
47.4 Signal Description
47.5 Product Dependencies
47.6 Functional Description
47.7 Register Summary
48 Secure Digital MultiMedia Card Controller (SDMMC)
48.1 Description
48.2 Embedded Characteristics
48.3 Reference Documents
48.4 Block Diagram
48.5 Application Block Diagram
48.6 Pin Name List
48.7 Product Dependencies
48.8 SD/SDIO Operating Mode
48.9 e.MMC Operating Mode
48.10 Register Summary
49 Image Sensor Interface (ISI)
49.1 Description
49.2 Embedded Characteristics
49.3 Block Diagram
49.4 Product Dependencies
49.5 Functional Description
49.6 Register Summary
50 Controller Area Network (CAN)
50.1 Description
50.2 Embedded Characteristics
50.3 Block Diagram
50.4 Application Block Diagram
50.5 I/O Lines Description
50.6 Product Dependencies
50.7 CAN Controller Features
50.8 Functional Description
50.9 Register Summary
51 Timer Counter (TC)
51.1 Description
51.2 Embedded Characteristics
51.3 Block Diagram
51.4 Pin List
51.5 Product Dependencies
51.6 Functional Description
51.7 Register Summary
52 Pulse Width Modulation Controller (PWM)
52.1 Description
52.2 Embedded Characteristics
52.3 Block Diagram
52.4 I/O Lines Description
52.5 Product Dependencies
52.6 Functional Description
52.7 Register Summary
53 Advanced Encryption Standard (AES)
53.1 Description
53.2 Embedded Characteristics
53.3 Product Dependencies
53.4 Functional Description
53.5 Register Summary
54 Secure Hash Algorithm (SHA)
54.1 Description
54.2 Embedded Characteristics
54.3 Product Dependencies
54.4 Functional Description
54.5 Register Summary
55 Triple Data Encryption Standard (TDES)
55.1 Description
55.2 Embedded Characteristics
55.3 Product Dependencies
55.4 Functional Description
55.5 Register Summary
56 Random Number Generator (TRNG)
56.1 Description
56.2 Embedded Characteristics
56.3 Block Diagram
56.4 Product Dependencies
56.5 Functional Description
56.6 Register Summary
57 Analog-to-Digital Controller (ADC)
57.1 Description
57.2 Embedded Characteristics
57.3 Block Diagram
57.4 Signal Description
57.5 Product Dependencies
57.6 Functional Description
57.7 Register Summary
58 Electrical Characteristics
58.1 Electrical Parameters Usage
58.2 Absolute Maximum Ratings
58.3 Recommended Operating Conditions
58.4 Recommended Power Supply Sequencing
58.5 I/O Characteristics
58.6 Digital Peripheral Timings
58.7 Analog Peripheral Characteristics
58.8 Power Consumption in Active Mode
58.9 Operation and Power Consumption in Low-Power Modes
59 Mechanical Characteristics
59.1 228-ball TFBGA Mechanical Characteristics
60 Marking
61 Ordering Information
62 Revision History
62.1 DS60001579G - 01/2024
62.2 DS60001579F - 09/2022
62.3 DS60001579E - 09/2021
62.4 DS60001579D - 09/2020
62.5 DS60001579C - 07/2020
62.6 DS60001579B - 02/2020
62.7 DS60001579A - 10/2019
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