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28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology
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PIC18F26Q24
PIC18F45Q24
PIC18F46Q24
PIC18F55Q24
PIC18F56Q24
Introduction
PIC18-Q24
Family Types
Features
Operating Characteristics
Memory
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
PIC18-Q24 Block Diagram
1
Packages
2
Pin Diagrams
2.1
***
2.2
***
2.3
***
2.4
***
2.5
***
2.6
***
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC18-Q24
Microcontrollers
4.1
Basic Connection Requirements
4.2
Power Supply Pins
4.3
Master Clear (
MCLR
) Pin
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
4.5
External Oscillator Pins
4.6
Unused I/Os
5
Register and Bit Naming Conventions
5.1
Register Names
5.2
Bit Names
5.3
Register and Bit Naming Exceptions
6
Register Legend
7
PIC18 CPU
7.1
System Arbitration
7.2
Memory Access Scheme
7.3
8x8 Hardware Multiplier
7.4
PIC18 Instruction Cycle
7.5
STATUS Register
7.6
Call Shadow Register
7.7
Register Definitions: System Arbiter
7.8
Register Summary - System Arbiter Control
8
Device Configuration
8.1
Configuration Settings
8.2
Enhanced Code Protection
8.3
User ID
8.4
Device ID and Revision ID
8.5
Register Definitions: Configuration Settings
8.6
Register Summary - Configuration Settings
8.7
Register Definitions: Device ID and Revision ID
8.8
Register Summary - DEVID/REVID
8.9
Register Definitions: Software ICSP Enable
9
Memory Organization
9.1
Program Memory Organization
9.2
Device Information Area
9.3
Device Configuration Information
9.4
Data Memory Organization
9.5
Data Addressing Modes
9.6
Data Memory and the Extended Instruction Set
9.7
Register Definitions: Memory Organization
9.8
Register Summary - Memory Organization
10
NVM - Nonvolatile Memory Module
10.1
Operations
10.2
Unlock Sequence
10.3
Program Flash Memory (PFM)
10.4
Data Flash Memory (DFM)
10.5
Register Definitions: NVM
10.6
Register Summary - NVM
11
VIC - Vectored Interrupt Controller Module
11.1
Overview
11.2
Interrupt Control and Status Registers
11.3
Interrupt Vector Table
11.4
Interrupt Priority
11.5
Interrupt Operation
11.6
Context Saving
11.7
Returning from Interrupt Service Routine (ISR)
11.8
Interrupt Latency
11.9
Interrupt Setup Procedure
11.10
External Interrupt Pins
11.11
Wake-Up from Sleep
11.12
Interrupt Compatibility
11.13
Register Definitions: Interrupt Control
11.14
Register Summary - Interrupts
12
OSC - Oscillator Module (With Fail-Safe Clock Monitor)
12.1
Clock Source Types
12.2
Clock Switching
12.3
Fail-Safe Clock Monitor (FSCM)
12.4
Active Clock Tuning (ACT)
12.5
Register Definitions: Oscillator Module
12.6
Register Summary - Oscillator Module
13
CRC - Cyclic Redundancy Check Module with Memory Scanner
13.1
Module Overview
13.2
Polynomial Implementation
13.3
Data Sources
13.4
CRC Check Value
13.5
CRC Interrupt
13.6
Configuring the CRC Module
13.7
Scanner Module Overview
13.8
Scanning Modes
13.9
Configuring the Scanner
13.10
Scanner Interrupt
13.11
Peripheral Module Disable
13.12
Register Definitions: CRC and Scanner Control
13.13
Register Summary - CRC
14
Resets
14.1
Power-on Reset (POR)
14.2
Brown-out Reset (BOR)
14.3
Low-Power Brown-out Reset (LPBOR)
14.4
MCLR
Reset
14.5
Windowed Watchdog Timer (WWDT) Reset
14.6
RESET Instruction
14.7
Stack Overflow/Underflow Reset
14.8
Programming Mode Exit
14.9
Power-up Timer (PWRT)
14.10
Start-Up Sequence
14.11
Determining the Cause of a Reset
14.12
Power Control (PCON0/PCON1) Registers
14.13
Register Definitions: Power Control
14.14
Register Summary - BOR Control and Power Control
15
WWDT - Windowed Watchdog Timer
15.1
Independent Clock Source
15.2
WWDT Operating Modes
15.3
Time-Out Period
15.4
Watchdog Window
15.5
Clearing the Watchdog Timer
15.6
Operation During Sleep
15.7
Register Definitions: Windowed Watchdog Timer Control
15.8
Register Summary - WDT Control
16
DMA - Direct Memory Access
16.1
DMA Registers
16.2
DMA Organization
16.3
DMA Interface
16.4
Disable DMA Message Transfer Upon Completion
16.5
Types of Hardware Triggers
16.6
Types of Data Transfers
16.7
DMA Interrupts
16.8
DMA Setup and Operation
16.9
Reset
16.10
Power-Saving Mode Operation
16.11
Example Setup Code
16.12
Register Overlay
16.13
Register Definitions: DMA
16.14
Register Summary - DMA
17
Power-Saving Modes
17.1
Doze Mode
17.2
Sleep Mode
17.3
Idle Mode
17.4
Peripheral Operation in Power-Saving Modes
17.5
Register Definitions: Power-Savings Control
17.6
Register Summary - Power-Savings Control
18
PMD - Peripheral Module Disable
18.1
Overview
18.2
Disabling a Module
18.3
Enabling a Module
18.4
Register Definitions: Peripheral Module Disable
18.5
Register Summary - PMD
19
I/O Ports
19.1
Overview
19.2
PORTx - Data Register
19.3
LATx - Output Latch
19.4
TRISx - Direction Control
19.5
ANSELx - Analog Control
19.6
WPUx - Weak Pull-Up Control
19.7
INLVLx - Input Threshold Control
19.8
SLRCONx - Slew Rate Control
19.9
ODCONx - Open-Drain Control
19.10
Edge Selectable Interrupt-on-Change
19.11
I
2
C Pad Control
19.12
I/O Priorities
19.13
MCLR
/V
PP
/RE3
Pin
19.14
Register Definitions: Port Control
19.15
Register Summary - I/O Ports
20
SRPORT – Signal Routing Port
20.1
Operation
20.2
Software Setup
20.3
Register Definitions: Signal Routing Port
20.4
Register Summary - Signal Routing Port
21
IOC - Interrupt-on-Change
21.1
Overview
21.2
Enabling the Module
21.3
Individual Pin Configuration
21.4
Interrupt Flags
21.5
Clearing Interrupt Flags
21.6
Operation in Sleep
21.7
Register Definitions: Interrupt-on-Change Control
21.8
Register Summary - Interrupt-on-Change Control
22
PPS - Peripheral Pin Select Module
22.1
Overview
22.2
PPS Inputs
22.3
PPS Outputs
22.4
Bidirectional Pins
22.5
PPS Lock
22.6
Operation During Sleep
22.7
Effects of a Reset
22.8
Register Definitions: Peripheral Pin Select (PPS)
22.9
Register Summary - Peripheral Pin Select Module
23
MVIO - Multi-Voltage I/O
23.1
Features
23.2
Module Overview
23.3
Operation
23.4
Register Definitions: MVIO
23.5
Register Summary - MVIO
24
CLC - Configurable Logic Cell
24.1
CLC Setup
24.2
CLC Interrupts
24.3
Effects of a Reset
24.4
Output Mirror Copies
24.5
Operation During Sleep
24.6
CLC Setup Steps
24.7
Register Overlay
24.8
Register Definitions: Configurable Logic Cell
24.9
Register Summary - CLC Control
25
CLKREF - Reference Clock Output Module
25.1
Clock Source
25.2
Programmable Clock Divider
25.3
Selectable Duty Cycle
25.4
Operation in Sleep Mode
25.5
Register Definitions: Reference Clock
25.6
Register Summary - Reference CLK
26
TMR0 - Timer0 Module
26.1
Timer0 Operation
26.2
Clock Selection
26.3
Timer0 Output and Interrupt
26.4
Operation During Sleep
26.5
Register Definitions: Timer0 Control
26.6
Register Summary - Timer0
27
TMR1 - Timer1 Module with Gate Control
27.1
Timer1 Operation
27.2
Clock Source Selection
27.3
Timer1 Prescaler
27.4
Secondary Oscillator
27.5
Timer1 Operation in Asynchronous Counter Mode
27.6
Timer1 16-Bit Read/Write Mode
27.7
Timer1 Gate
27.8
Timer1 Interrupt
27.9
Timer1 Operation During Sleep
27.10
CCP Capture/Compare Time Base
27.11
CCP Special Event Trigger
27.12
Peripheral Module Disable
27.13
Register Definitions: Timer1 Control
27.14
Register Summary - Timer1
28
TMR2 - Timer2 Module
28.1
Timer2 Operation
28.2
Timer2 Output
28.3
External Reset Sources
28.4
Timer2 Interrupt
28.5
PSYNC Bit
28.6
CSYNC Bit
28.7
Operating Modes
28.8
Operation Examples
28.9
Timer2 Operation During Sleep
28.10
Register Definitions: Timer2 Control
28.11
Register Summary - Timer2
29
UTMR - Universal Timer Module
29.1
Module Nomenclature
29.2
Clock Source Selection
29.3
UTMR Prescaler
29.4
UTMR Operation
29.5
UTMR Output Modes
29.6
Interrupt and DMA Triggers
29.7
Operation During Sleep
29.8
Chaining Counter Timers
29.9
Register Definitions: Universal Timer
29.10
Register Summary - Universal Timer
30
CCP - Capture/Compare/PWM Module
30.1
CCP Module Configuration
30.2
Capture Mode
30.3
Compare Mode
30.4
PWM Overview
30.5
Register Definitions: CCP Control
30.6
Register Summary - CCP Control
31
Capture, Compare, and PWM Timers Selection
31.1
Register Definitions: Capture, Compare, and PWM Timers Selection
31.2
Register Summary - Capture, Compare, and PWM Timers Selection
32
PWM - Pulse-Width Modulator with Compare
32.1
Output Slices
32.2
Period Timer
32.3
Clock Sources
32.4
External Period Resets
32.5
Buffered Period and Parameter Registers
32.6
Synchronizing Multiple PWMs
32.7
Interrupts
32.8
Operation During Sleep
32.9
Register Definitions: PWM Control
32.10
Register Summary - PWM
33
CWG - Complementary Waveform Generator Module
33.1
Fundamental Operation
33.2
Operating Modes
33.3
Clock Source
33.4
Selectable Input Sources
33.5
Output Control
33.6
Dead-Band Control
33.7
Rising Edge and Reverse Dead Band
33.8
Falling Edge and Forward Dead Band
33.9
Dead-Band Jitter
33.10
Auto-Shutdown
33.11
Auto-Shutdown Restart
33.12
Operation During Sleep
33.13
Configuring the CWG
33.14
Register Definitions: CWG Control
33.15
Register Summary - CWG
34
NCO - Numerically Controlled Oscillator Module
34.1
NCO Operation
34.2
Fixed Duty Cycle Mode
34.3
Pulse Frequency Mode
34.4
Output Polarity Control
34.5
Interrupts
34.6
Effects of a Reset
34.7
Operation in Sleep
34.8
Register Definitions: NCO
34.9
Register Summary - NCO
35
UART - Universal Asynchronous Receiver Transmitter with Protocol Support
35.1
UART I/O Pin Configuration
35.2
UART Asynchronous Modes
35.3
DMX Mode (Full-Featured UARTs Only)
35.4
LIN Modes (Full-Featured UARTs Only)
35.5
DALI Mode (Full-Featured UARTs Only)
35.6
General Purpose Manchester (Full-Featured UARTs Only)
35.7
Polarity
35.8
Stop Bits
35.9
Operation After FIFO Overflow
35.10
Receive and Transmit Buffers
35.11
Flow Control
35.12
Checksum (Full-Featured UARTs Only)
35.13
Collision Detection (Full-Featured UARTs Only)
35.14
RX/TX Activity Time-Out
35.15
Clock Accuracy with Asynchronous Operation
35.16
UART Baud Rate Generator
35.17
Transmitting a Break
35.18
Receiving a Break
35.19
UART Operation During Sleep
35.20
Register Definitions: UART
35.21
Register Summary - UART
36
SPI - Serial Peripheral Interface Module
36.1
SPI Controls
36.2
SPI Operation
36.3
Host Mode
36.4
Client Mode
36.5
SPI Operation in Sleep Mode
36.6
SPI Interrupts
36.7
Register Definitions: Serial Peripheral Interface
36.8
Register Summary - SPI Control
37
I
2
C - Inter-Integrated Circuit Module
37.1
I
2
C Features
37.2
I
2
C Terminology
37.3
I
2
C Module Overview
37.4
I
2
C Operation
37.5
Register Definitions: I
2
C Control
37.6
Register Summary - I
2
C
38
HLVD - High/Low-Voltage Detect
38.1
Operation
38.2
Setup
38.3
Current Consumption
38.4
HLVD Start-Up Time
38.5
Applications
38.6
Operation During Sleep
38.7
Operation During Idle and Doze Modes
38.8
Effects of a Reset
38.9
Register Definitions: HLVD Control
38.10
Register Summary - HLVD
39
FVR - Fixed Voltage Reference
39.1
Independent Gain Amplifiers
39.2
FVR Stabilization Period
39.3
Register Definitions: FVR
39.4
Register Summary - FVR
40
Temperature Indicator Module
40.1
Module Operation
40.2
Temperature Calculation
40.3
ADC Acquisition Time
40.4
Register Definitions: Temperature Indicator
40.5
Register Summary - Temperature Indicator
41
ADC - Analog-to-Digital Converter with Computation Module
41.1
ADC Configuration
41.2
ADC Operation
41.3
ADC Acquisition Requirements
41.4
ADC Charge Pump
41.5
Computation Operation
41.6
Register Definitions: ADC Control
41.7
Register Summary - ADC
42
DAC - Digital-to-Analog Converter Module - 8-Bit
42.1
Output Voltage Selection
42.2
Ratiometric Output Level
42.3
Operation During Sleep
42.4
Effects of a Reset
42.5
Register Definitions: DAC Control
42.6
Register Summary - DAC
43
CMP - Comparator Module
43.1
Comparator Overview
43.2
Comparator Control
43.3
Comparator Output Synchronization
43.4
Comparator Hysteresis
43.5
Comparator Interrupt
43.6
Comparator Positive Input Selection
43.7
Comparator Negative Input Selection
43.8
Comparator Response Time
43.9
Analog Input Connection Considerations
43.10
Operation in Sleep Mode
43.11
ADC Auto-Trigger Source
43.12
Register Definitions: Comparator Control
43.13
Register Summary - Comparator
44
ZCD - Zero-Cross Detection Module
44.1
External Resistor Selection
44.2
ZCD Logic Output
44.3
ZCD Logic Polarity
44.4
ZCD Interrupts
44.5
Correction for Z
CPINV
Offset
44.6
Handling V
PEAK
Variations
44.7
Operation During Sleep
44.8
Effects of a Reset
44.9
Disabling the ZCD Module
44.10
Register Definitions: ZCD Control
44.11
Register Summary - ZCD
45
Instruction Set Summary
45.1
Standard Instruction Set
45.2
Extended Instruction Set
46
ICSP™ - In-Circuit Serial Programming™
46.1
High-Voltage Programming Entry Mode
46.2
Low-Voltage Programming Entry Mode
46.3
Common Programming Interfaces
47
Register Summary
48
Electrical Specifications
48.1
Absolute Maximum Ratings
(†)
48.2
Standard Operating Conditions
48.3
DC Characteristics
48.4
AC Characteristics
49
DC and AC Characteristics Graphs and Tables
49.1
I
DD
Graphs
49.2
I
PD
Graphs
49.3
Wake from Sleep Graphs
49.4
MCLR Reset Graphs
49.5
Power-Up Reset Graphs
49.6
Power-On Reset Graphs
49.7
Brown-Out Reset Graphs
49.8
Windowed Watchdog Timer Graphs
49.9
High/Low-Voltage Detect Graphs
49.10
I/O Graphs
49.11
Fixed Voltage Reference Graphs
49.12
Analog-to-Digital Converter (10-bit) Graphs
49.13
Temperature Sensor Graphs
49.14
Comparator Graphs
49.15
Digital-to-Analog Converter (8-bit) Graphs
49.16
Zero-Cross Detection Graphs
50
Packaging Information
50.1
Package Details
51
Appendix A: Revision History
52
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature
