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28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology
Description
Core Features
Memory
Operating Characteristics
Power-Saving Operation Modes
eXtreme Low-Power (XLP) Features
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
PIC18(L)F26/45/46K40 Family Types
Pin Allocation Tables
1 Pin Diagrams
1.1 ***
1.2 ***
1.3 ***
1.4 ***
1.5 ***
2 Device Overview
2.1 New Core Features
2.2 Other Special Features
2.3 Details on Individual Family Members
2.4 Register and Bit Naming Conventions
3 Guidelines for Getting Started with PIC18(L)F26/45/46K40 Microcontrollers
3.1 Basic Connection Requirements
3.2 Power Supply Pins
3.3 Master Clear (MCLR) Pin
3.4 In-Circuit Serial Programming™ (ICSP™) Pins
3.5 External Oscillator Pins
3.6 Unused I/Os
4 Device Configuration
4.1 Configuration Words
4.2 Code Protection
4.3 Write Protection
4.4 User ID
4.5 Device ID and Revision ID
4.6 Register Summary - Configuration Words
4.7 Register Definitions: Configuration Words
4.8 Register Summary - Device and Revision
4.9 Register Definitions: Device and Revision
5 OSC - Oscillator Module
5.1 Overview
5.2 Clock Source Types
5.3 Clock Switching
5.4 Fail-Safe Clock Monitor
5.5 Register Summary - OSC
5.6 Register Definitions: Oscillator Control
6 REFCLK - Reference Clock Output Module
6.1 Clock Source
6.2 Programmable Clock Divider
6.3 Selectable Duty Cycle
6.4 Operation in Sleep Mode
6.5 Register Summary - Reference CLK
6.6 Register Definitions: Reference Clock
7 Power-Saving Operation Modes
7.1 Doze Mode
7.2 Sleep Mode
7.3 Peripheral Operation in Power-Saving Modes
7.4 Register Summary - Power Savings Control
7.5 Register Definitions: Power Savings Control
8 PMD - Peripheral Module Disable
8.1 Disabling a Module
8.2 Enabling a Module
8.3 Register Summary - PMD
8.4 Register Definitions: Peripheral Module Disable
9 Resets
9.1 Power-on Reset (POR)
9.2 Brown-out Reset (BOR)
9.3 Low-Power Brown-out Reset (LPBOR)
9.4 MCLR Reset
9.5 Windowed Watchdog Timer (WWDT) Reset
9.6 RESET Instruction
9.7 Stack Overflow/Underflow Reset
9.8 Programming Mode Exit
9.9 Power-up Timer (PWRT)
9.10 Start-up Sequence
9.11 Determining the Cause of a Reset
9.12 Power Control (PCON0) Register
9.13 Register Summary - BOR Control and Power Control
9.14 Register Definitions: Power Control
10 WWDT - Windowed Watchdog Timer
10.1 Independent Clock Source
10.2 WWDT Operating Modes
10.3 Time-out Period
10.4 Watchdog Window
10.5 Clearing the WWDT
10.6 Operation During Sleep
10.7 Register Summary - WDT Control
10.8 Register Definitions: Windowed Watchdog Timer Control
11 Memory Organization
11.1 Program Memory Organization
11.2 PIC18 Instruction Cycle
11.3 Data Memory Organization
11.4 Data Addressing Modes
11.5 Data Memory and the Extended Instruction Set
11.6 PIC18 Instruction Execution and the Extended Instruction Set
11.7 Register Summary - Memory and Status
11.8 Register Definitions: Memory and Status
12 NVM - Nonvolatile Memory Control
12.1 Program Flash Memory
12.2 User ID, Device ID and Configuration Word Access
12.3 Data EEPROM Memory
12.4 Register Summary - NVM Control
12.5 Register Definitions: Nonvolatile Memory
13 8x8 Hardware Multiplier
13.1 Introduction
13.2 Operation
13.3 Register Summary - 8x8 Hardware Multiplier
13.4 Register Definitions: 8x8 Hardware Multiplier
14 CRC - Cyclic Redundancy Check Module with Memory Scanner
14.1 CRC Module Overview
14.2 CRC Functional Overview
14.3 CRC Polynomial Implementation
14.4 CRC Data Sources
14.5 CRC Check Value
14.6 CRC Interrupt
14.7 Configuring the CRC
14.8 Program Memory Scan Configuration
14.9 Scanner Interrupt
14.10 Scanning Modes
14.11 Register Summary - CRC
14.12 Register Definitions: CRC and Scanner Control
15 Interrupts
15.1 Midrange Compatibility
15.2 Interrupt Priority
15.3 Interrupt Response
15.4 INTCON Registers
15.5 PIR Registers
15.6 PIE Registers
15.7 IPR Registers
15.8 INTn Pin Interrupts
15.9 TMR0 Interrupt
15.10 Interrupt-on-Change
15.11 Context Saving During Interrupts
15.12 Register Summary - Interrupt Control
15.13 Register Definitions: Interrupt Control
16 I/O Ports
16.1 I/O Priorities
16.2 PORTx Registers
16.3 PORTE Registers
16.4 Register Summary - Input/Output
16.5 Register Definitions: Port Control
17 Interrupt-on-Change
17.1 Features
17.2 Overview
17.3 Block Diagram
17.4 Enabling the Module
17.5 Individual Pin Configuration
17.6 Interrupt Flags
17.7 Clearing Interrupt Flags
17.8 Operation in Sleep
17.9 Register Summary - Interrupt-on-Change
17.10 Register Definitions: Interrupt-on-Change Control
18 PPS - Peripheral Pin Select Module
18.1 PPS Inputs
18.2 PPS Outputs
18.3 Bidirectional Pins
18.4 PPS Lock
18.5 PPS One-Way Lock
18.6 Operation During Sleep
18.7 Effects of a Reset
18.8 Register Summary - PPS
18.9 Register Definitions: PPS Input and Output Selection
19 TMR0 - Timer0 Module
19.1 Timer0 Operation
19.2 Clock Selection
19.3 Timer0 Output and Interrupt
19.4 Operation During Sleep
19.5 Register Summary - Timer0
19.6 Register Definitions: Timer0 Control
20 TMR1 - Timer1 Module with Gate Control
20.1 Timer1 Operation
20.2 Clock Source Selection
20.3 Timer1 Prescaler
20.4 Secondary Oscillator
20.5 Timer1 Operation in Asynchronous Counter Mode
20.6 Timer1 16-Bit Read/Write Mode
20.7 Timer1 Gate
20.8 Timer1 Interrupt
20.9 Timer1 Operation During Sleep
20.10 CCP Capture/Compare Time Base
20.11 CCP Special Event Trigger
20.12 Peripheral Module Disable
20.13 Register Summary - Timer1
20.14 Register Definitions: Timer1
21 TMR2 - Timer2 Module
21.1 Timer2 Operation
21.2 Timer2 Output
21.3 External Reset Sources
21.4 Timer2 Interrupt
21.5 Operating Modes
21.6 Operation Examples
21.7 Timer2 Operation During Sleep
21.8 Register Summary - Timer2
21.9 Register Definitions: Timer2 Control
22 Capture/Compare/PWM Module
22.1 CCP Module Configuration
22.2 Capture Mode
22.3 Compare Mode
22.4 PWM Overview
22.5 Register Summary - CCP Control
22.6 Register Definitions: CCP Control
23 PWM - Pulse-Width Modulation
23.1 Fundamental Operation
23.2 PWM Output Polarity
23.3 PWM Period
23.4 PWM Duty Cycle
23.5 PWM Resolution
23.6 Operation in Sleep Mode
23.7 Changes in System Clock Frequency
23.8 Effects of Reset
23.9 Setup for PWM Operation Using PWMx Output Pins
23.10 Setup for PWM Operation to Other Device Peripherals
23.11 Register Summary - Registers Associated with PWM
23.12 Register Definitions: PWM Control
24 ZCD - Zero-Cross Detection Module
24.1 External Resistor Selection
24.2 ZCD Logic Output
24.3 ZCD Logic Polarity
24.4 ZCD Interrupts
24.5 Correction for ZCPINV Offset
24.6 Handling VPEAK Variations
24.7 Operation During Sleep
24.8 Effects of a Reset
24.9 Disabling the ZCD Module
24.10 Register Summary - ZCD Control
24.11 Register Definitions: ZCD Control
25 CWG - Complementary Waveform Generator
25.1 Fundamental Operation
25.2 Operating Modes
25.3 Start-up Considerations
25.4 Clock Source
25.5 Selectable Input Sources
25.6 Output Control
25.7 Dead-Band Control
25.8 Rising Edge and Reverse Dead Band
25.9 Falling Edge and Forward Dead Band
25.10 Dead-Band Jitter
25.11 Auto-Shutdown
25.12 Operation During Sleep
25.13 Configuring the CWG
25.14 Register Summary - CWG Control
25.15 Register Definitions: CWG Control
26 DSM - Data Signal Modulator Module
26.1 DSM Operation
26.2 Modulator Signal Sources
26.3 Carrier Signal Sources
26.4 Carrier Synchronization
26.5 Carrier Source Polarity Select
26.6 Programmable Modulator Data
26.7 Modulated Output Polarity
26.8 Operation in Sleep Mode
26.9 Effects of a Reset
26.10 Peripheral Module Disable
26.11 Register Summary - DSM
26.12 Register Definitions: Modulation Control
27 MSSP - Host Synchronous Serial Port Module
27.1 SPI Mode Overview
27.2 I2C Mode Overview
27.3 Baud Rate Generator
27.4 Register Definitions: MSSP Control
27.5 Register Summary - MSSP Control
28 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
28.1 EUSART Asynchronous Mode
28.2 Clock Accuracy with Asynchronous Operation
28.3 EUSART Baud Rate Generator (BRG)
28.4 EUSART Synchronous Mode
28.5 EUSART Operation During Sleep
28.6 Register Definitions: EUSART Control
28.7 Register Summary - EUSART
29 FVR - Fixed Voltage Reference
29.1 Independent Gain Amplifiers
29.2 FVR Stabilization Period
29.3 Register Summary - FVR
29.4 Register Definitions: FVR Control
30 Temperature Indicator Module
30.1 Circuit Operation
30.2 Minimum Operating VDD
30.3 Temperature Output
30.4 ADC Acquisition Time
31 DAC - 5-Bit Digital-to-Analog Converter
31.1 Output Voltage Selection
31.2 Ratiometric Output Level
31.3 DAC Voltage Reference Output
31.4 Operation During Sleep
31.5 Effects of a Reset
31.6 Register Summary - DAC Control
31.7 Register Definitions: DAC Control
32 ADCC - Analog-to-Digital Converter with Computation Module
32.1 ADC Configuration
32.2 ADC Operation
32.3 ADC Acquisition Requirements
32.4 Capacitive Voltage Divider (CVD) Features
32.5 Computation Operation
32.6 Register Summary - ADC Control
32.7 Register Definitions: ADC Control
33 CMP - Comparator Module
33.1 Comparator Overview
33.2 Comparator Control
33.3 Comparator Hysteresis
33.4 Operation with Timer1 Gate
33.5 Comparator Interrupt
33.6 Comparator Positive Input Selection
33.7 Comparator Negative Input Selection
33.8 Comparator Response Time
33.9 Analog Input Connection Considerations
33.10 CWG1 Auto-Shutdown Source
33.11 ADC Auto-Trigger Source
33.12 Even Numbered Timers Reset
33.13 Operation in Sleep Mode
33.14 Register Summary - Comparator
33.15 Register Definitions: Comparator Control
34 HLVD - High/Low-Voltage Detect
34.1 Operation
34.2 Setup
34.3 Current Consumption
34.4 HLVD Start-up Time
34.5 Applications
34.6 Operation During Sleep
34.7 Operation During Idle and Doze Modes
34.8 Effects of a Reset
34.9 Register Summary - HLVD
34.10 Register Definitions: HLVD Control
35 Register Summary
36 ICSP™ - In-Circuit Serial Programming™
36.1 High-Voltage Programming Entry Mode
36.2 Low-Voltage Programming Entry Mode
36.3 Common Programming Interfaces
37 Instruction Set Summary
37.1 Standard Instruction Set
37.2 Extended Instruction Set
38 Electrical Specifications
38.1 Absolute Maximum Ratings(†)
38.2 Standard Operating Conditions
38.3 DC Characteristics
38.4 AC Characteristics
39 DC and AC Characteristics Graphs and Tables
39.1 Graphs
40 Packaging Information
40.1 Package Details
41 Appendix A: Revision History
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