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32-bit Arm Cortex-M23 Low Power MCU with Security, Safety, CAN-FD, Full Speed USB, Touch and Advanced Analog
32-bit Arm® Cortex®-M23 MCU with Security, Functional Safety (FuSa), CAN-FD, Full-Speed USB, Enhanced Touch, and Advanced Analog
1 Guidelines for Getting Started
1.1 Basic Connection Requirements
1.2 Decoupling Capacitors
1.3 External Reset (RESET) Pin
1.4 Debugging or Programming Pins
1.5 JTAG
1.6 External Oscillator Pins
1.7 Unused I/Os
1.8 Considerations When Interfacing to Remotely Powered Circuits
1.9 Designing for High-Speed Peripherals
2 Configuration Summary
3 Ordering Information
4 Block Diagram
5 Pinout and Packaging
5.1 48-pin TQFP and 48-pin VQFN
5.2 64-pin TQFP and 64-pin VQFN
5.3 100-pin TQFP
6 Signal Description
7 Power Supplies and Startup Considerations
7.1 Power Domain Overview
7.2 Power Domain Constraints
7.3 Power Up
7.4 Analog Peripherals Considerations
7.5 Device Startup
8 Product Mapping
9 Peripherals
9.1 Register Description
10 Processor and Architecture
10.1 Processor and Architecture
10.2 Arm Cortex-M23 Configuration
10.3 Nested Vector Interrupt Controller
10.4 NVIC Interrupt Mapping
10.5 High Speed Bus
10.6 Bus Matrix Connectivity
11 Memories
11.1 Embedded Memories
11.2 Physical Memory Map
11.3 SRAM Memory Configuration
11.4 Flash Memories
11.5 Unique ID (UID)
12 PIC32CM SG00/GC00 Security Features
12.1 Data Flash
12.2 TrustRAM
12.3 Arm TrustZone for ARMv8-M
13 Implementation Defined Attribution Unit (IDAU)
13.1 Overview
13.2 IDAU Regions IDS
13.3 IDAU Region Types
13.4 Secure and Secure Always On Region Types
13.5 IDAU Programmable Regions
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13.6 IDAU Watermark Regions
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13.7 H2PB Exempt Main Regions
13.8 IDAU Regions Configuration
13.9 Configuration Write Lock
13.10 Peripheral Dependencies
13.11 Register Summary
14 System Bus AHB - APB Bridge (H2PB)
14.1 Overview
14.2 Features
14.3 Functional Description
14.4 Peripheral Dependencies
14.5 Register Summary
15 Multi-Channel RAM Controller (MCRAMC)
15.1 Overview
15.2 Features
15.3 Block Diagram
15.4 Functional Description
15.5 Peripheral Dependencies
15.6 Register Summary
16 Peripheral Access Controller (PAC)
16.1 Overview
16.2 Features
16.3 Debug Operation
16.4 Register Access Protection
16.5 Functional Description
16.6 Peripheral Dependencies
16.7 Register Summary
17 Device Service Unit (DSU)
17.1 Overview
17.2 Features
17.3 DSU Block Diagram
17.4 Signal Description
17.5 Debug Operation
17.6 Programming
17.7 Device Identification
17.8 Peripheral Dependencies
17.9 Register Summary
18 Clock Distribution System
18.1 Clock Distribution
18.2 Clock System Features
18.3 Synchronous and Asynchronous Clocks
18.4 Register Synchronization
18.5 Enabling a Peripheral
18.6 On Demand Clock Requests
18.7 Power Consumption Versus Speed
18.8 Clocks after Reset
19 Oscillator Controller (OSCCTRL)
19.1 Overview
19.2 Features
19.3 OSCCTRL Block Diagram
19.4 Signal Descriptions
19.5 Functional Description
19.6 Peripheral Dependencies
19.7 Register Summary
20 Generic Clock Controller (GCLK)
20.1 Overview
20.2 Features
20.3 Block Diagram
20.4 Signal Description
20.5 Functional Description
20.6 Peripheral Dependencies
20.7 GCLK Peripheral Channel Control Mapping
20.8 Register Summary
21 Main Clock (MCLK)
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Functional Description
21.5 Peripheral Dependencies
21.6 MCLK AHB/APB Clock Enable Peripheral Mapping
21.7 Register Summary
22 32 KHz Oscillators Controller (OSC32KCTRL)
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Signal Description
22.5 Functional Description
22.6 Peripheral Dependencies
22.7 Register Summary
23 Watchdog Timer (WDT)
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Functional Description
23.5 Peripheral Dependencies
23.6 Register Summary
24 Frequency Meter (FREQM)
24.1 Overview
24.2 Features
24.3 Block Diagram
24.4 Signal Description
24.5 Clocks
24.6 Functional Description
24.7 Peripheral Dependencies
24.8 Register Summary
25 Real-Time Counter (RTC)
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Signal Description
25.5 Functional Description
25.6 Peripheral Dependencies
25.7 Register Summary - MODE0
25.8 Register Summary - MODE1
25.9 Register Summary - MODE2
25.10 Register Summary
26 Direct Memory Access Controller (DMAC)
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Functional Description
26.5 Peripheral Dependencies
26.6 Register Summary
26 DMA Descriptor Register Summary
27 Supply Controller (SUPC)
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Signals Description
27.5 Functional Description
27.6 Peripheral Dependencies
27.7 Register Summary
28 Power Manager (PM)
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Functional Description
28.5 Peripheral Dependencies
28.6 Register Summary
29 Reset Controller (RSTC)
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signals Description
29.5 Functional Description
29.6 Peripheral Dependencies
29.7 Register Summary
30 External Interrupt Controller (EIC)
30.1 Overview
30.2 Features
30.3 Block Diagram
30.4 Signal Description
30.5 Interrupts
30.6 Events
30.7 Sleep Mode Operation
30.8 Secure Access Right
30.9 Synchronization
30.10 Peripheral Dependencies
30.11 Register Summary
31 Non-Volatile Memory Controller (NVMCTRL)
31.1 Flash Controller, Write
31.2 Flash Controller, Read
31.3 Peripheral Dependencies
31.4 Peripheral Dependencies
31.5 Register Summary
31.6 Register Summary
32 Event System (EVSYS)
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Power Management
32.5 Clocks
32.6 Functional Description
32.7 Peripheral Dependencies
32.8 Register Summary
33 I/O Pin Controller (PORT)
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 Signal Description
33.5 I/O Lines
33.6 Clocks
33.7 Power Management
33.8 Debug Operation
33.9 Register Access Protection
33.10 Analog Connections
33.11 PIC32CM SG Specific Secure Access Protection
33.12 Functional Description
33.13 Peripheral Dependencies
33.14 Register Summary
34 Serial Communication Interface (SERCOM)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Functional Description
34.5 Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
34.6 SERCOM Serial Peripheral Interface (SPI)
34.7 SERCOM I2C
34.8 Peripheral Dependencies
34.9 Register Summary - USART
34.10 Register Summary - SPI
34.11 Register Summary - I2CM
34.12 Register Summary - I2CS
35 Controller Area Network (CAN)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Signal Description
35.5 Functional Description
35.6 Peripheral Dependencies
35.7 Register Summary
35 Rx Buffer and FIFO Element Register Summary
35 Tx Buffer Element Register Summary
35 Tx Event FIFO Element Register Summary
35 Standard Message ID Filter Element Register Summary
35 Extended Message ID Filter Element Register Summary
36 Universal Serial Bus (USB)
36.1 Overview
36.2 Features
36.3 USB Block Diagram
36.4 Signal Description
36.5 Functional Description
36.6 Peripheral Dependencies
36.7 Register Summary
36.8 Register Summary - DEVICE
36.9 Register Summary - HOST
36 USB Descriptor Register Summary
37 Configurable Custom Logic (CCL)
37.1 Overview
37.2 Features
37.3 Block Diagram
37.4 Signal Description
37.5 I/O Lines
37.6 Power Management
37.7 Clocks
37.8 Events
37.9 Debug Operation
37.10 Register Access Protection
37.11 Functional Description
37.12 Events
37.13 Sleep Mode Operation
37.14 Peripheral Dependencies
37.15 Register Summary
38 Analog to Digital Converter (ADC)
38.1 Overview
38.2 Features
38.3 Block Diagram
38.4 Signal Description
38.5 Functional Description
38.6 Peripheral Dependencies
38.7 Register Summary
39 Analog Comparator (AC)
39.1 Overview
39.2 Features
39.3 Block Diagram
39.4 Analog Connections
39.5 Functional Description
39.6 Peripheral Dependencies
39.7 Register Summary
40 Timer/Counter for Control Applications (TCC)
40.1 Overview
40.2 Features
40.3 Block Diagram
40.4 Signal Description
40.5 Functional Description
40.6 Peripheral Dependencies
40.7 Register Summary
41 TrustRAM (TRAM)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Functional Description
41.5 Peripheral Dependencies
41.6 Register Summary
42 Peripheral Touch Controller (PTC)
42.1 Overview
42.2 Features
42.3 Block Diagram
42.4 Signal Description
42.5 Peripheral Dependencies
42.6 Functional Description
42.7 Peripheral Dependencies
43 Hardware Security Module Lite (HSM-Lite)
43.1 Overview
43.2 Features
43.3 Operation
43.4 Cryptographic Accelerators
43.5 TRNG
43.6 PUF Interface
43.7 Peripheral Dependencies
43.8 Register Summary
44 Anti-Tamper Module (AT)
44.1 Overview
45 Physically Uncloneable Function (PUF)
45.1 Overview
46 Electrical Characteristics
46.1 Absolute Maximum Electrical Characteristics
46.2 CPU Electrical Characteristics
46.3 Power Supply
46.4 Active Power
46.5 Idle Power
46.6 Standby Power
46.7 Hibernate Power
46.8 Backup Power
46.9 OFF Power
46.10 Wake-Up Timing
46.11 Peripheral Active Power
46.12 I/O Pin Electrical Characteristics
46.13 Internal Voltage Reference Electrical Specifications (IVREF)
46.14 Maximum Clock Frequencies
46.15 XOSC Electrical Characteristics
46.16 XOSC32K Electrical Characteristics
46.17 OSCULP32K Electrical Characteristics
46.18 DFLL-FDPLL Electrical Characteristics
46.19 Analog-to-Digital Converter (ADC) Electrical Specifications
46.20 Comparator (AC) Electrical Characteristics
46.21 Peripheral Touch Controller (PTC) Electrical Characteristics
46.22 Serial Peripheral Interface (SPI) Timings Electrical Characteristics
46.23 Universal Asynchronous Receiver/Transmitter (UART) Electrical Characteristics
46.24 I2C Electrical Characteristics
46.25 Controller Area Network (CAN) Electrical Characteristics
46.26 Timer/Counter Controller (TCC) Electrical Characteristics
46.27 Universal Serial Bus (USB) Electrical Characteristics
46.28 Flash Controller Electrical Characteristics
46.29 Frequency Meter (FREQM) Electrical Characteristics
46.30 JTAG Electrical Characteristics
46.31 SWD 2-Wire Electrical Characteristics
46.32 Configurable Custom Logic (CCL) Electrical Specifications
46.33 User LDO Electrical Specifications
46.34 Multi-Channel Ram Controller (MCRAMC) Electrical Specifications
47 Packaging Information
47.1 Package Marking Information
47.2 Package Drawings
47.3 Soldering Profile
48 Schematic Checklist
48.1 Introduction
49 Common Conventions
49.1 Numerical Notation
49.2 Memory Size and Type
49.3 Frequency and Time
49.4 Registers and Bits
50 Acronyms and Abbreviations
51 Revision History
Microchip Information
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