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PIC32CX-BZ3 and WBZ35x Family Data Sheet
Introduction
PIC32CX-BZ3 SoC Family Features
WBZ35x Module Features
Acronyms and Abbreviations
1 Ordering Information
1.1 PIC32CX-BZ3 SoC Ordering Information
1.2 WBZ35x Module Ordering Information
2 Configuration Summary
3 PIC32CX-BZ3 SoC Description
3.1 PIC32CX-BZ3 SoC Block Diagram
3.2 Pinout Diagram
4 WBZ35x Module Description
4.1 Pinout Diagram
4.2 Basic Connection Requirement
4.3 WBZ35x Module Placement Guidelines
4.4 WBZ35x Module Routing Guidelines
4.5 WBZ35x Module RF Considerations
4.6 WBZ35x Module Antenna Considerations
4.7 WBZ35x Module Reflow Profile Information
4.8 WBZ35x Module Assembly Considerations
5 Pinout and Signal Descriptions List
6 I/O Ports and Peripheral Pin Select (PPS)
6.1 Overview
6.2 Features
6.3 Block Diagram
6.4 Parallel I/O (PIO) Ports
6.5 Peripheral Pin Select (PPS)
6.6 Peripheral Multiplexing
6.7 Function Priority for Device Pins
6.8 Operation in Power Saving Modes
6.9 Results of Various Resets
6.10 Port Register Summary
6.11 Register Description
6.12 Peripheral Pin Select (PPS) Input Mapping Register Summary
6.13 Peripheral Pin Select (PPS) Output Mapping Register Summary
6.14 Register Description
7 Power Subsystem
7.1 Block Diagram
7.2 VDD Voltage Domain Overview
7.3 VDD-AON Power Domain Overview
7.4 VDDBKUPCORE Power Domain
7.5 PMU Controller
7.6 Voltage Regulators
7.7 Power Supply Modes
7.8 Typical Power Supply Connection for SoC
7.9 Typical Power Supply Connection for WBZ35x Module
7.10 Power-Up Sequence
8 Product Memory Mapping Overview
8.1 Embedded Memories
8.2 Physical Memory Map
8.3 Boot ROM
8.4 Flash Memory Parameters
8.5 eFuse Memory
8.6 SRAM Memory Configuration
8.7 Boot Flash Device Configuration Word
8.8 Boot Flash Code Protection Register
Boot Flash Code Protection Register
9 Processor and Architecture
9.1 Cortex M4F Processor
9.2 Nested Vector Interrupt Controller (NVIC)
9.3 High-Speed Bus System
10 Prefetch Cache (PCHE)
10.1 Overview
10.2 Features
10.3 Overview
10.4 Product Dependencies
10.5 Prefetch Behavior
10.6 Configurations
10.7 Predictive Prefetch Behavior
10.8 Coherency Support
10.9 Effects of Reset
10.10 Error Conditions
10.11 Register Summary
10.12 Register Description
11 Cortex M Cache Controller (CMCC)
11.1 Overview
11.2 Features
11.3 Block Diagram
11.4 Signal Description
11.5 Product Dependencies
11.6 Functional Description
11.7 RAM Properties
11.8 Register Summary
11.9 Register Description
12 Secure Boot ROM
12.1 Overview
12.2 Features
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
12.6 Application Transition
13 eFuse Controller
13.1 Overview
13.2 Hardware Mode
13.3 eFuse Programming
13.4 eFuse Auto-Loading
13.5 Security Keys
13.6 Counters
13.7 Register Summary
13.8 Register Description
14 Security Features
14.1 Overview
14.2 Features
14.3 Reference Documentation
14.4 Interface
14.5 Description
14.6 Register Summary
14.7 Register Description
15 Flash Controller (FC)
15.1 Overview
15.2 Features
15.3 Functional Block Diagram
15.4 Product Dependencies
15.5 Flash Memory Addressing
15.6 Memory Configuration
15.7 Boot Flash Memory (BFM) Partitions
15.8 Program Flash Memory (PFM) Partitions
15.9 Error Correcting Code (ECC) and Flash Programming
15.10 Interrupts
15.11 Error Detection
15.12 NVMKEY Register Unlocking Sequence
15.13 Word Programming
15.14 Quad Word Programming
15.15 Row Programming
15.16 Page Erase
15.17 Program Flash Memory (PFM) Erase
15.18 Device Code Protection Bit (CP)
15.19 Effects of Various Resets
15.20 Register Summary
15.21 Register Description
16 Device Service Unit (DSU)
16.1 Overview
16.2 Features
16.3 DSU Block Diagram
16.4 Signal Description
16.5 Product Dependencies
16.6 Debug Operation
16.7 Chip Erase
16.8 Programming
16.9 Intellectual Property Protection
16.10 Device Identification
16.11 Functional Description
16.12 Register Summary
16.13 Register Description
17 Clock and Reset Unit (CRU)
17.1 Overview
17.2 Features
17.3 Clock System
17.4 Resets
17.5 Register Summary
17.6 Register Description
18 Power Management Unit (PMU)
18.1 Overview
18.2 Features
18.3 Functional Description
18.4 Register Summary
18.5 Register Description
18.6 Register Summary
18.7 Register Description
19 Watchdog Timer (WDT)
19.1 Overview
19.2 Features
19.3 Block Diagram
19.4 Watchdog Timer Operation
19.5 Interrupt and Reset Generation
19.6 Operation in Debug and Power-Saving Modes
19.7 Effects of Various Resets
19.8 Register Summary
19.9 Register Description
20 Deadman Timer (DMT)
20.1 Overview
20.2 Features
20.3 Block Diagram
20.4 DMT Operation
20.5 Register Summary
20.6 Register Description
21 RAM Error Correction Code (RAMECC)
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Signal Description
21.5 Product Dependencies
21.6 Functional Description
21.7 Register Summary
21.8 Register Description
22 System Configuration and Register Locking (CFG)
22.1 Overview
22.2 Features
22.3 Modes of Operation
22.4 Locking and Unlocking the System Configuration Registers
22.5 NMI Events
22.6 Register Locking
22.7 Effects of Various Resets
22.8 Register Summary
22.9 Register Description
23 Peripheral Module Disable (PMD)
23.1 Overview
23.2 Enabling Peripherals
23.3 Controlling Configuration Changes
23.4 PMD Register Summary
23.5 Register Description
24 Peripheral Access Controller (PAC)
24.1 Overview
24.2 Features
24.3 Block Diagram
24.4 Product Dependencies
24.5 Functional Description
24.6 Register Summary
24.7 Register Description
25 Real-Time Counter and Calendar (RTCC)
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Signal Description
25.5 Product Dependencies
25.6 Functional Description
25.7 Register Summary - Mode 0 - 32-Bit Counter
25.8 Register Description - Mode 0 - 32-Bit Counter
25.9 Register Summary - Mode 0 - 32-Bit Counter
25.10 Register Description - Mode 1 - 16-Bit Counter
25.11 Register Summary - Mode 0 - 32-Bit Counter
25.12 Register Description - Mode 2 - Clock/Calendar
26 Direct Memory Access Controller (DMAC)
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Signal Description
26.5 Product Dependencies
26.6 Functional Description
26.7 Register Summary
26.8 Register Description
26.9 DMAC Register Summary (SRAM)
26.10 Register Description - SRAM
27 External Interrupt Controller (EIC)
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Signal Description
27.5 Product Dependencies
27.6 Functional Description
27.7 Register Summary
27.8 Register Description
28 Configurable Custom Logic (CCL)
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Signal Description
28.5 Product Dependencies
28.6 Functional Description
28.7 Register Summary
28.8 Register Description
29 Frequency Meter (FREQM)
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signal Description
29.5 Product Dependencies
29.6 Functional Description
29.7 Register Summary
29.8 Register Description
30 Event System (EVSYS)
30.1 Overview
30.2 Features
30.3 Block Diagram
30.4 Signal Description
30.5 Product Dependencies
30.6 Functional Description
30.7 Register Summary
30.8 Register Description
31 Serial Communication Interface (SERCOM)
31.1 Overview
31.2 Features
31.3 Block Diagram
31.4 Signal Description
31.5 Product Dependencies
31.6 Functional Description
32 SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
32.1 Overview
32.2 USART Features
32.3 Block Diagram
32.4 Signal Description
32.5 Product Dependencies
32.6 Functional Description
32.7 Register Summary
32.8 Register Description
33 SERCOM Serial Peripheral Interface (SERCOM SPI)
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 Signal Description
33.5 Product Dependencies
33.6 Functional Description
33.7 Register Summary
33.8 Register Description
34 SERCOM Inter-Integrated Circuit (SERCOM I2C)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Signal Description
34.5 Product Dependencies
34.6 Functional Description
34.7 Register Summary
34.8 Register Description - I2C Client
34.9 Register Summary
34.10 Register Description - I2C Client
35 Quad Serial Peripheral Interface (QSPI)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Signal Description
35.5 Product Dependencies
35.6 Functional Description
35.7 Register Summary
35.8 Register Description
36 Analog-to-Digital Converter (ADC)
36.1 Overview
36.2 Features
36.3 Block Diagram
36.4 ADC Operation
36.5 ADC Module Configuration
36.6 Additional ADC Functions
36.7 Interrupts
36.8 Power-Saving Modes of Operation
36.9 Effects of Reset
36.10 Transfer Function
36.11 ADC Sampling Requirements
36.12 Register Summary
36.13 Register Description
37 Capacitive Voltage Divider (CVD) Controller for Touch Sensing
37.1 Overview
37.2 Features
37.3 Configuration
37.4 Block Diagram
37.5 CVD Module Operation
37.6 Register Summary
37.7 Register Description
38 Analog Comparators (AC)
38.1 Overview
38.2 Features
38.3 Block Diagram
38.4 Product Dependencies
38.5 Functional Description
38.6 Register Summary
38.7 Register Description
39 Digital-to-Analog Converter (DAC)
39.1 Overview
39.2 Features
39.3 Block Diagram
39.4 DAC Timing Diagram
39.5 Functional Description
39.6 Register Summary
40 Timer/Counter (TC)
40.1 Overview
40.2 Features
40.3 Block Diagram
40.4 Signal Description
40.5 Product Dependencies
40.6 Functional Description
40.7 Register Summary - 8-bit Mode
40.8 Register Description - 8-Bit Mode
40.9 Register Summary - 16-bit Mode
40.10 Register Description - 16-Bit Mode
40.11 Register Summary - 32-bit Mode
40.12 Register Description - 32-Bit Mode
41 Timer/Counter for Control Applications (TCC)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Signal Description
41.5 Product Dependencies
41.6 Functional Description
41.7 Register Summary
41.8 Register Description
42 Zigbee Bluetooth Radio Subsystem (ZBT)
42.1 Overview
42.2 Features
42.3 Wireless Subsystem Top Level Diagram
42.4 Analog RF Front-End
42.5 Digital Front-end
42.6 Bluetooth Low Energy Link Controller
42.7 Zigbee Subsystem
42.8 Radio Arbiter
42.9 Register Banks
42.10 Coexistence Interface
43 Electrical Characteristics
43.1 Absolute Maximum Ratings
43.2 Operating Conditions
43.3 DC Electrical Characteristics
43.4 Thermal Specifications
43.5 Power Supply DC Module Electrical Specifications
43.6 Active Current Consumption DC Electrical Specifications
43.7 Idle Current Consumption DC Electrical Specifications
43.8 Sleep Current Consumption DC Electrical Specifications
43.9 Deep Sleep Current Consumption DC Electrical Specifications
43.10 XDS (Extreme Deep Sleep) Current Consumption DC Electrical Specifications
43.11 Wake-Up Timing from Low Power Modes AC Electrical Specifications
43.12 I/O PIN AC/DC Electrical Specifications
43.13 External XTAL and Clock AC Electrical Specifications
43.14 XOSC32 AC Electrical Specifications
43.15 Low Power Internal 32 kHz RC Oscillator AC Electrical Specifications
43.16 DAC Module Electrical Specifications
43.17 ADC Electrical Specifications
43.18 Comparator AC Electrical Specifications
43.19 SPI Module Electrical Specifications
43.20 UART AC Electrical Specifications
43.21 I2C Module Electrical Specifications
43.22 QSPI Module Electrical Specifications
43.23 TCx Timer Capture Module AC Electrical Specifications
43.24 TCCx Timer Capture Module AC Electrical Specifications
43.25 FLASH NVM AC Electrical Specifications
43.26 Frequency Meter AC Electrical Specifications
43.27 SWD 2-Wire AC Electrical Specifications
43.28 FRC Clock AC Electrical Specifications
43.29 Bluetooth Low Energy RF Characteristics
43.30 Zigbee RF Characteristics
44 Packaging Information
44.1 PIC32CX-BZ3 SoC Packaging Information
44.2 WBZ35x Module Packaging Information
45 Appendix A: Regulatory Approval
45.1 United States
45.2 Canada
45.3 Europe
45.4 Japan
45.5 Korea
45.6 Taiwan
45.7 China
45.8 UKCA (UK Conformity Assessed)
45.9 Other Regulatory Information
46 Appendix B: Acronyms and Abbreviations
47 Document Revision History
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