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32-bit Connectivity MCU with Integrated Security PIC32CZ CA80/CA90 Family
Up to 8 MB Flash, 1 MB SRAM, Hardware Security Module, Secure Boot, Floating Point Unit (FPU), Advanced Analog, Gigabit Ethernet, HS USB, CAN FD, and Peripheral Touch Controller (PTC)
1 Configuration Summary
2 Guidelines for Getting Started
2.1 Basic Connection Requirements
2.2 Decoupling Capacitors
2.3 External Reset (RESET) Pin
2.4 Power and Temperature Considerations
2.5 Debugging or Programming Pins
2.6 JTAG
2.7 Trace
2.8 External Oscillator Pins
2.9 Unused I/Os
2.10 Considerations When Interfacing to Remotely Powered Circuits
2.11 Designing for High-Speed Peripherals
3 Ordering Information
4 Block Diagram
5 Pinout
5.1 100-Pin TQFP EP Thin Plastic Quad Flatpack
5.2 144-Pin TQFP EP Thin Plastic Quad Flatpack
5.3 144-Pin TFBGA Thin Fine Pitch Ball Grid Array
5.4 176-Pin TFBGA Thin Fine Pitch Ball Grid Array
5.5 208-Pin TFBGA Thin Fine Pitch Ball Grid Array
6 Signal Description
7 Power Supplies and Startup Considerations
7.1 Power Domain Overview
7.2 Power Domain Constraints
7.3 Power Up
7.4 Power-On Reset and Brown-Out Reset
7.5 Analog Peripherals Considerations
7.6 Device Startup
8 Product Mapping
8.1 Code Address Space
8.2 SRAM Address Space
8.3 Peripheral Address Space
8.4 External RAM Address Space
8.5 Peripheral Bus A Address Map
8.6 Peripheral Bus B Address Map
8.7 Peripheral Bus C Address Map
8.8 Peripheral Bus D Address Map
8.9 Peripheral Bus E Address Map
8.10 Peripheral Bus F Address Map
8.11 Peripheral Bus AHB Address Map
8.12 Flash CFM Configuration Address Map
9 Peripherals
9.1 Register Description
10 Processor and Architecture
10.1 Arm Cortex-M7
10.2 Nested Vectored Interrupt Controller
10.3 High-Speed Bus
11 Memories
11.1 Embedded Memories
11.2 Physical Memory Map
11.3 SRAM Memory Configuration
11.4 Configuration Flash Memory (CFM)
11.5 Unique ID (UID)
12 Hardware Security Module (HSM)
12.1 Features
12.2 Performance
12.3 For More Information
13 Multi-Channel RAM Controller (MCRAMC)
13.1 Overview
13.2 Features
13.3 Block Diagram
13.4 Peripheral Dependencies
13.5 Functional Description
13.6 Register Summary
14 Tightly Coupled Memory with ECC (TCM)
14.1 Overview
14.2 Features
14.3 Block Diagram
14.4 Peripheral Dependencies
14.5 Functional Description
14.6 Register Summary
15 Peripheral Access Controller (PAC)
15.1 Overview
15.2 Features
15.3 Block Diagram
15.4 Peripheral Dependencies
15.5 Functional Description
15.6 Register Summary
16 Device Service Unit (DSU)
16.1 Overview
16.2 Features
16.3 Block Diagram
16.4 Signal Description
16.5 Peripheral Dependencies
16.6 Indexing
16.7 Debug Operation
16.8 Multi-Processor Support
16.9 Programming
16.10 Security Enforcement
16.11 Device Identification
16.12 Functional Description
16.13 Register Summary
16.14 DATA Register Summary in MBIST Mode
17 Clock Distribution System
17.1 Clock Distribution
17.2 Synchronous and Asynchronous Clocks
17.3 Register Synchronization
17.4 Enabling a Peripheral
17.5 On Demand Clock Requests
17.6 Power Consumption Versus Speed
17.7 Clocks after Reset
18 Oscillator Controller (OSCCTRL)
18.1 Overview
18.2 Features
18.3 OSCCTRL Block Diagram
18.4 Signal Descriptions
18.5 Peripheral Dependencies
18.6 Functional Description
18.7 Register Summary
19 32 KHz Oscillators Controller (OSC32KCTRL)
19.1 Overview
19.2 Features
19.3 Block Diagram
19.4 Signal Description
19.5 Peripheral Dependencies
19.6 Functional Description
19.7 Register Summary
20 Generic Clock Controller (GCLK)
20.1 Overview
20.2 Features
20.3 Block Diagram
20.4 Signal Description
20.5 Peripheral Dependencies
20.6 Functional Description
20.7 Register Summary
21 Main Clock (MCLK)
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Peripheral Dependencies
21.5 Functional Description
21.6 Register Summary
22 Watchdog Timer (WDT)
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Peripheral Dependencies
22.5 Functional Description
22.6 Register Summary
23 Frequency Meter (FREQM)
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Signal Description
23.5 Peripheral Dependencies
23.6 Clocks
23.7 Functional Description
23.8 Register Summary
24 Real-Time Counter (RTC)
24.1 Overview
24.2 Features
24.3 Block Diagram
24.4 Signal Description
24.5 Peripheral Dependencies
24.6 Functional Description
24.7 Register Summary - 32-bit Counter Mode
24.8 Register Summary - 16-bit Counter Mode
24.9 Register Summary Clock/Calendar Mode
25 Direct Memory Access Controller (DMAC)
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Peripheral Dependencies
25.5 Indexing
25.6 DMA Event/Trigger Mapping
25.7 Applications
25.8 Module Description
25.9 Register Summary
25.10 Channelk Register Summary, k = 0,1,...,15
26 Supply Controller (SUPC)
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Signals Description
26.5 Peripheral Dependencies
26.6 Functional Description
26.7 Register Summary
27 Power Manager (PM)
27.1 Features
27.2 Block Diagram
27.3 Peripheral Dependencies
27.4 Functional Description
27.5 Sleep Modes
27.6 Basic Operation
27.7 Sleepwalking
27.8 Wake-Up Time
27.9 Standby with Power Domain Gating
27.10 Interrupts
27.11 Debug Operation
27.12 Register Summary
28 Reset Controller (RSTC)
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Signals Description
28.5 Peripheral Dependencies
28.6 Functional Description
28.7 Register Summary
29 External Interrupt Controller (EIC)
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signal Description
29.5 Peripheral Dependencies
29.6 Functional Description
29.7 Register Summary
30 MLB Media Local Bus (MLB)
30.1 Overview
30.2 Features
30.3 Block Diagram
30.4 Signal Description
30.5 Peripheral Dependencies
30.6 MediaLB Concept
30.7 MediaLB Protocol
30.8 Internal Flow Description
30.9 MLB Functional Description
Enter a short description of your concept here (optional).
30.10 Register Summary
31 Non-Volatile Memory Controller (NVMCTRL)
31.1 Block Diagram
31.2 Flash Controller, Write
31.3 Flash Controller, Read
32 Gigabit Ethernet Media Access Controller (GMAC / ETH)
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Signal Interface
32.5 Peripheral Dependencies
32.6 Functional Description
32.7 Programming Interface
32.8 Register Summary
33 Event System (EVSYS)
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 Power Management
33.5 Clocks
33.6 Functional Description
33.7 Register Summary
34 I/O Pin Controller (PORT)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Signal Description
34.5 Peripheral Dependencies
34.6 I/O Lines
34.7 Clocks
34.8 CPU AHB Bus
34.9 Power Management
34.10 Debug Operation
34.11 Functional Description
34.12 Register Summary
35 Serial Communication Interface (SERCOM)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Peripheral Dependencies
35.5 Functional Description
35.6 Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
35.7 SERCOM Serial Peripheral Interface (SPI)
35.8 SERCOM I2C
36 Serial Quad Interface (SQI)
36.1 Overview
36.2 Features
36.3 Block Diagram
36.4 Functional Description
36.5 Register Summary
37 Hi-Speed Universal Serial Bus (USB)
37.1 Overview
37.2 Features
37.3 Block Diagram
37.4 Signal Description
37.5 Peripheral Dependencies
37.6 Functional Description
37.7 Register Summary: USB Common Registers
37.8 Register Summary: USB Endpoint0 Common Registers
37.9 Register Summary: USB Host Mode Only Registers
37.10 Register Summary: Home Mode Endpoint0 Registers
37.11 Register Summary: USB Host Mode Endpoint1-7 Registers
37.12 Register Summary: Device Mode Only Common Registers
37.13 Register Summary: Device Mode Endpoint0 Registers
37.14 Register Summary: Device Mode Endpoint1-7 Registers
37.15 Register Summary: USB PHY Registers
38 Controller Area Network (CAN)
38.1 Overview
38.2 Features
38.3 Block Diagram
38.4 Signal Description
38.5 Peripheral Dependencies
38.6 Functional Description
38.7 Register Summary
39 External Bus Interface (EBI)
39.1 Overview
39.2 Features
39.3 EBI Block Diagram
39.4 I/O Lines Description
39.5 Application Example
39.6 Peripheral Dependencies
39.7 Functional Description
39.8 Register Summary
40 SD/MMC Host Controller (SDHC)
40.1 Overview
40.2 Features
40.3 Block Diagram
40.4 Connection Diagram
40.5 Signal Description
40.6 Peripheral Dependencies
40.7 Functional Description
40.8 Register Summary
41 True Random Number Generator (TRNG)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Clocks
41.5 Functional Description
41.6 Register Summary
42 Analog-to-Digital Converter (ADC)
42.1 Overview
42.2 Features
42.3 Block Diagram
42.4 Signal Description
42.5 Peripheral Dependencies
42.6 Functional Description
42.7 Register Summary
43 Analog Comparators (AC)
43.1 Overview
43.2 Features
43.3 Block Diagram
43.4 Analog Connections
43.5 Peripheral Dependencies
43.6 Functional Description
43.7 Register Summary
44 Timer/Counter for Control Applications (TCC)
44.1 Overview
44.2 Features
44.3 Block Diagram
44.4 Signal Description
44.5 Peripheral Dependencies
44.6 Functional Description
44.7 Register Summary
45 TrustRAM (TRAM)
45.1 Overview
45.2 Features
45.3 Block Diagram
45.4 Peripheral Dependencies
45.5 Functional Description
45.6 Register Summary
46 Peripheral Touch Controller (PTC)
46.1 Overview
46.2 Features
46.3 Block Diagram
46.4 Signal Description
46.5 Peripheral Dependencies
46.6 Functional Description
47 SPI/I2S/I8S Controller
47.1 Overview
47.2 Features
47.3 Block Diagram
47.4 Peripheral Dependencies
47.5 Functional Description
47.6 Register Summary
48 Electrical Characteristics
48.1 Absolute Maximum Electrical Characteristics
48.2 CPU Electrical Characteristics
48.3 Power Supply
48.4 MCU Active Power
48.5 MCU Idle Power
48.6 MCU Standby Power
48.7 MCU Hibernate Power
48.8 MCU OFF Power
48.9 Wake-Up Timing
48.10 Peripheral Active Power
48.11 I/O Pin Electrical Specifications
48.12 Internal Voltage Reference Electrical Specifications
48.13 Maximum Clock Frequencies
48.14 External Oscillator (XOSC) Electrical Specifications
48.15 External 32.768 kHz Oscillator (XOSC32) Electrical Specifications
48.16 Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Electrical Specifications
48.17 DFLL/FPLL Electrical Specifications
48.18 Analog-to-Digital Converter (ADC) Electrical Specifications
48.19 Comparator Electrical Specifications
48.20 Peripheral Touch Controller (PTC) Electrical Specifications
48.21 Serial Peripheral Interface (SPI) Electrical Specifications
48.22 UART Electrical Specifications
48.23 I2S Electrical Specifications
48.24 I2C Electrical Specifications
48.25 SQI/QSPI Electrical Specifications
48.26 Controller Area Network (CAN) Electrical Specifications
48.27 Timer Counter for Control Applications (TCC) Electrical Specifications
48.28 Universal Serial Bus (USB) Electrical Specifications
48.29 Non-Volatile Memory Controller (NVM) Electrical Specifications
48.30 Gigabit Ethernet MAC (GMAC/ETH) Electrical Specifications
48.31 Frequency Meter (FREQM) Electrical Specifications
48.32 True Random Number Generator (TRNG) Electrical Specifications
48.33 SD/MMC Host Controller (SDHC) Electrical Specifications
48.34 External Bus Interface (EBI) Electrical Specifications
48.35 Media Local Bus (MLB) Electrical Specifications
48.36 JTAG Electrical Specifications
48.37 SWD 2-Wire Electrical Specifications
49 Packaging Information
49.1 Package Marking Information
49.2 Package Drawings
49.3 Soldering Profile
50 Schematic Checklist
50.1 Introduction
51 Common Conventions
51.1 Numerical Notation
51.2 Memory Size and Type
51.3 Frequency and Time
51.4 Registers and Bits
52 Acronyms and Abbreviations
53 Revision History
Microchip Information
Trademarks
Legal Notice
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