Overview

High-speed ADCs are implemented on 3.3V dsPIC33A MCUs, which can reach conversion rates of 40 MSPS. This document explains how to store the high-speed ADC data stream in RAM for further processing.

The maximum conversion rate of 40 MSPS requires a 320 MHz ADC input clock (typically provided by Clock Generator 6) and the minimum sampling time (when the SAMC bits are zero in the ADxCHyCON or ADxCHyCON1 register).

The holding capacitor (C_HOLD) for these ADCs is 1 pF, and the internal interconnect resistance (R_IC) on the die is 120 Ω. To charge C_HOLD with a 0.5 LSB error, the 9RC time is required for a 12-bit ADC, which limits the input signal impedance. To convert at the maximum 40 MSPS speed (80 MHz ADC clock cycle or T_AD = 12.5 ns), when the SAMC bits are zero (the sampling time is 0.5 T_AD = 6.25 ns), the signal source impedance must not exceed:

$R_{SIGNAL} < \frac{0.5 \times T_{AD}}{9 \times C_{HOLD}} - R_{IC} = 574\Omega$

Microcontroller modules can operate in different clock domains. In such cases, signals between different frequency domains pass through synchronizers, which are typically implemented using several latches that delay the signals. If the clock of one domain is asynchronous to the clock in another domain, the synchronization delay may vary depending on the signal edge location. However, if both domains are clocked from the same source (that is, the clocks are synchronous), the synchronization delay becomes stable (always the same).

It is important to have the same clock source for both the ADC and the module that triggers the ADC to ensure consistent timing (synchronization delay) for the trigger.

Several methods are available for storing high-speed ADC data streams into RAM:

• Using multiple ADC channels triggered from one source
• Using DMA transfers
• Moving conversion results by the CPU