2 Interrupt Controller Overview

The tinyAVR 0- and 1-series, and megaAVR 0-series Interrupt Controller has support for multiple individual Interrupt Requests (IRQs), with dedicated interrupt vectors. This helps reduce latency when an interrupt is triggered.

When an interrupt is enabled and the interrupt condition occurs, the CPU will receive an IRQ from the Interrupt Controller. Based on the interrupt's priority level and the priority level of any ongoing Interrupt Service Routine (ISR), the IRQ is either acknowledged (and its ISR is executed) or kept pending. See Figure 2-1 for a graphical representation of the Interrupt Controller interaction.

Figure 2-1. Interrupt Controller Flowchart
The Interrupt Controller decides the order of execution for pending ISRs by the combination of the interrupts priority level and vector address. The hardwired vector addresses and different priority modes are configurable from the CPUINT registers, with the following available priority levels:
  1. Non-Maskable Interrupts
  2. Level 1 Priority Interrupts
  3. Level 0 Priority Interrupts
Refer to the device datasheet for the interrupt vector mapping.

Interrupt Flags

The Global Interrupt Enable flag (I-flag) must be set for IRQs to be generated, with Non-Maskable Interrupts as the only exception. Information on these can be found under Non-Maskable Interrupts.

The majority of interrupt flags must be cleared in the corresponding ISR. This is because some interrupt sources share interrupt vectors. Other flags are cleared by hardware when entering the ISR or reading a data register. For detailed information, refer to each peripheral's chapter in the device datasheet.

Interrupt Latency

The CPU's interrupt latency is determined by the number of clock cycles required for the following actions:

  1. Complete the ongoing instruction.
    • 1 - 3 clock cycles, dependent on instruction time.
  2. Push the program counter on the stack.
    • 2 clock cycles.
  3. Execute the jump instruction stored in the interrupt vector table.
    • 2 - 3 clock cycles, dependent on Flash size. See Table 2-1.
      Table 2-1. Interrupt Jump Instruction
      Flash sizeJump instructionJump Execution Time
      ≤ 8kBRJMP2 clock cycles
      > 8kBJMP3 clock cycles

The total interrupt latency will be five to eight clock cycles, depending on the parameters listed above. See the AVR Instruction Set Manual for more information.

If the device is in Sleep mode, the response time increases by five clock cycles, in addition to the CPU start-up time from the used Sleep mode.