1 Silicon Issue Summary

Legend

-
Erratum is not applicable.
X
Erratum is applicable.
PeripheralShort DescriptionValid for Silicon Revision
Rev. A3(1)Rev. A4
Device Some Reserved Fuse Bits Are ‘1’ XX
CRC Check During Reset Initialization Is not Functional XX
CCL The LINK Input Source Selection for LUT3 Is not Functional on 28- and 32-Pin Devices XX
CLKCTRL PLL Status not Working as Expected XX
DAC DAC Output Buffer Lifetime Drift XX
NVMCTRL Flash Multi-Page Erase Can Erase Write Protected Section XX
PORT Digital Input on Pin Automatically Disabled When Pin Selected for Analog Input XX
RSTCTRL BOD Registers not Reset When UPDI Is Enabled XX
TCA Restart Will Reset Counter Direction in NORMAL and FRQ Mode XX
TCB CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode XX
TCD Asynchronous Input Events not Working When TCD Counter Prescaler Is Used XX
CMPAEN Controls All WOx for Alternative Pin Functions XX
Halting TCD and Wait for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used XX
TWI The Output Pin Override Does not Function as Expected XX
Flush Non-Functional XX
USART Open-Drain Mode Does not Work When TXD Is Configured as Output XX
Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode XX
ZCD All ZCD Output Selection Bits Are Tied to the ZCD0 Bit XX
Note:
  1. This revision is the initial release of the silicon.