33.5.1 ADCON0

ADC Control Register 0

Note:

This bit requires the ON bit to be set.
If cleared by software while a conversion is in progress, the results of the conversion up to this point will be transferred to ADRES and the state machine will be reset, but the ADIF interrupt flag bit will not be set; filter and threshold operations will not be performed.

Name:	ADCON0
Offset:	0x1D26


Bit	7	6	5	4	3	2	1	0
	ON	CONT		CS	FM[1:0]		IC	GO
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W/HC/HS
Reset	0	0		0	0	0	1	0

Bit 7 – ON ADC Enable

Value	Description
1	ADC is enabled
0	ADC is disabled

Bit 6 – CONT ADC Continuous Operation Enable

Value	Description
1	GO is retriggered upon completion of each conversion trigger until ADTIF is set (if SOI is set) or until GO is cleared (regardless of the value of SOI)
0	ADC is cleared upon completion of each conversion trigger

Bit 4 – CS ADC Clock Selection

Value	Description
1	Clock supplied from ADCRC dedicated oscillator
0	Clock supplied by F_OSC, divided according to the ADCLK register

Bits 3:2 – FM[1:0] ADC Results Format/Alignment Selection

Value	Name	Description
x1	IC = `0`	ADRES and ADPREV data are right justified
x0	IC = `0`	ADRES and ADPREV data are left justified, zero-filled
11	IC = `1`	ADRES and ADPREV data are right justified, sign bit
10	IC = `1`	ADRES and ADPREV data are left justified, sign bit, zero-filled
01	IC = `1`	ADRES and ADPREV data are right justified, two’s complement
00	IC = `1`	ADRES and ADPREV data are left justified, two’s complement, zero-filled

Bit 1 – IC ADC Input Configuration

Value	Description
1	ADC is operating in Differential mode
0	ADC is operating in Single-Ended mode

Bit 0 – GO ADC Conversion Status^(1,2)

Value	Description
1	ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the CONT bit.
0	ADC conversion completed/not in progress

This bit requires the ON bit to be set. If cleared by software while a conversion is in progress, the results of the conversion up to this point will be transferred to ADRES and the state machine will be reset, but the ADIF interrupt flag bit will not be set; filter and threshold operations will not be performed.