32.3 EUSART Baud Rate Generator (BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operations. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit selects 16-bit mode.

The SPxBRGH:SPxBRGL register pair determines the period of the free-running baud rate timer. In Asynchronous mode, the multiplier of the baud rate period is determined by both the BRGH and the BRG16 bits. In Synchronous mode, the BRGH bit is ignored.

Table 32-1 contains the formulas for determining the baud rate. Equation 32-1 provides a sample calculation for determining the baud rate and baud rate error.

Typical baud rates and error values for various Asynchronous modes have been computed and are shown in the table below. It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. The BRGH bit is used to achieve very high baud rates.

Writing a new value to the SPxBRGH:SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.

If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this, check the status of the Receive Idle Flag (RCIDL) bit to make sure the receive operation is idle before changing the system clock.

For a device with F_OSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

$DesiredBaudrate=\frac{F_{OSC}}{64\times (SPxBRG+1)}$

Solving for SPxBRG:

$SPxBRG=\frac{F_{OSC}}{64\times DesiredBaudrate}-1$

$SPxBRG=\frac{16000000}{64\times 9600}-1$

$SPxBRG=25.042\simeq 25$

$CalculatedBaudrate=\frac{16000000}{64\times (25+1)}$

$CalculatedBaudrate=9615$

$Error=\frac{CalculatedBaudrate-DesiredBaudrate}{DesiredBaudrate}$

$Error=\frac{9615-9600}{9600}$

$Error=0.16\%$