55.24 SPI Electrical Specifications

Figure 55-1. SPI Host Module (CPHA = 0) Timing Diagrams
Figure 55-2. SPI Host Module (CPHA = 1) Timing Diagrams
Table 55-32. SPI Module Host Mode Electrical Specifications (1)
AC CHARACTERISTICSStandard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
MSP_1FSCKSCK Frequency——15MHzVDD = 1.8V, CLOAD = 20 pF(MAX)
——20MHzVDD = 3.3V, CLOAD=20pF(MAX)
MSP_3TSCLSCK Output Low Time1/(2*FSCK)——ns—
MSP_5TSCHSCK Output High Time1/(2*FSCK)——ns—
MSP_7TSCFSCK & MOSI Output Fall Time——DI_27nsDI_27: Refer to I/O Pin Electrical Specifications
MSP_9TSCRSCK & MOSI Output Rise Time——DI_25nsDI_25: Refer to I/O Pin Electrical Specifications
MSP_11TMOVMOSI Data Output Valid after SCK——9nsVDD(min), CLOAD=20pF(MAX)
MSP_13TMOHMOSI hold after SCK0——ns
MSP_15TMISMISO Setup Time of Data Input to SCK18——ns
MSP_17TMIHMISO Hold Time of Data Input to SCK0——ns
MSP_19SPI_GCLKSERCOM SPI input clock freq, GCLK_SPI——FCLK_23MHzFCLK_23: Refer to Maximum Clock Frequencies Electrical Specifications
Note:
  1. Assumes VDD(min) and 20 pF external load on all SPIx pins unless otherwise noted.
Figure 55-3. SPI Client Module (CPHA = 0) Timing Diagrams
Figure 55-4. SPI Client Module (CPHA = 1) Timing Diagrams
Table 55-33. SPI Module Client Mode Electrical Specifications (1)
AC CHARACTERISTICSStandard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
SSP_1FSCKSCK Frequency——15MHzVDD=1.8V, CLOAD=20pF(MAX)
——20MHzVDD=3.3V, CLOAD=20pF(MAX)
SSP_3TSCLSCK Output Low Time1/(2*FSCK)——ns—
SSP_5TSCHSCK Output High Time1/(2*FSCK)——ns—
SSP_7TSCFSCK & MOSI Output Fall Time——DI_27nsDI_27: Refer to I/O Pin Electrical Specifications
SSP_9TSCRSCK & MOSI Output Rise Time——DI_25nsDI_25: Refer to I/O Pin Electrical Specifications
SSP_11TSOVMOSI Data Output Valid after SCK——15.7nsVDD(min),

CLOAD=20pF(MAX)

FCLK_5: Refer to

Maximum Clock Frequencies Electrical Specifications

SSP_13TSOHMOSI hold after SCK0——ns
SSP_15TSISMISO Setup Time of Data Input to SCK7.5——ns
SSP_17TSIHMISO Hold Time of Data Input to SCK4——ns
SSP_19TSSSSS setup to SCK (PRELOADEN=1)(2/FCLK_5)+(1/FSCK)——ns
SS setup to SCK (PRELOADEN=0)1/FSCK——ns
SSP_21TSSHSS hold after SCK Client1/(2*FSCK)——ns
SSP_23SPI_GCLKSERCOM SPI input clock freq, GCLK_SPI——FCLK_23MHzFCLK_23: Refer to Maximum Clock Frequencies Electrical Specifications
Note:
  1. Assumes VDD(min) and 20 pF external load on all SPI pins unless otherwise noted.