55.24 SPI Electrical Specifications

Figure 55-1. SPI Host Module (CPHA = 0) Timing Diagrams
Figure 55-2. SPI Host Module (CPHA = 1) Timing Diagrams
Table 55-32. SPI Module Host Mode Electrical Specifications (1)
AC CHARACTERISTICS Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
MSP_1 FSCK SCK Frequency — — 15 MHz VDD = 1.8V, CLOAD = 20 pF(MAX)
— — 20 MHz VDD = 3.3V, CLOAD=20pF(MAX)
MSP_3 TSCL SCK Output Low Time 1/(2*FSCK) — — ns —
MSP_5 TSCH SCK Output High Time 1/(2*FSCK) — — ns —
MSP_7 TSCF SCK & MOSI Output Fall Time — — DI_27 ns DI_27: Refer to I/O Pin Electrical Specifications
MSP_9 TSCR SCK & MOSI Output Rise Time — — DI_25 ns DI_25: Refer to I/O Pin Electrical Specifications
MSP_11 TMOV MOSI Data Output Valid after SCK — — 9 ns VDD(min), CLOAD=20pF(MAX)
MSP_13 TMOH MOSI hold after SCK 0 — — ns
MSP_15 TMIS MISO Setup Time of Data Input to SCK 18 — — ns
MSP_17 TMIH MISO Hold Time of Data Input to SCK 0 — — ns
MSP_19 SPI_GCLK SERCOM SPI input clock freq, GCLK_SPI — — FCLK_23 MHz FCLK_23: Refer to Maximum Clock Frequencies Electrical Specifications
Note:
  1. Assumes VDD(min) and 20 pF external load on all SPIx pins unless otherwise noted.
Figure 55-3. SPI Client Module (CPHA = 0) Timing Diagrams
Figure 55-4. SPI Client Module (CPHA = 1) Timing Diagrams
Table 55-33. SPI Module Client Mode Electrical Specifications (1)
AC CHARACTERISTICS Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
SSP_1 FSCK SCK Frequency — — 15 MHz VDD=1.8V, CLOAD=20pF(MAX)
— — 20 MHz VDD=3.3V, CLOAD=20pF(MAX)
SSP_3 TSCL SCK Output Low Time 1/(2*FSCK) — — ns —
SSP_5 TSCH SCK Output High Time 1/(2*FSCK) — — ns —
SSP_7 TSCF SCK & MOSI Output Fall Time — — DI_27 ns DI_27: Refer to I/O Pin Electrical Specifications
SSP_9 TSCR SCK & MOSI Output Rise Time — — DI_25 ns DI_25: Refer to I/O Pin Electrical Specifications
SSP_11 TSOV MOSI Data Output Valid after SCK — — 15.7 ns VDD(min),

CLOAD=20pF(MAX)

FCLK_5: Refer to

Maximum Clock Frequencies Electrical Specifications
SSP_13 TSOH MOSI hold after SCK 0 — — ns
SSP_15 TSIS MISO Setup Time of Data Input to SCK 7.5 — — ns
SSP_17 TSIH MISO Hold Time of Data Input to SCK 4 — — ns
SSP_19 TSSS SS setup to SCK (PRELOADEN=1) (2/FCLK_5)+(1/FSCK) — — ns
SS setup to SCK (PRELOADEN=0) 1/FSCK — — ns
SSP_21 TSSH SS hold after SCK Client 1/(2*FSCK) — — ns
SSP_23 SPI_GCLK SERCOM SPI input clock freq, GCLK_SPI — — FCLK_23 MHz FCLK_23: Refer to Maximum Clock Frequencies Electrical Specifications
Note:
  1. Assumes VDD(min) and 20 pF external load on all SPI pins unless otherwise noted.