45.6.2.1 Initialization

The following registers are enable-protected, meaning that they can only be written when the TCC is disabled(CTRLA.ENABLE=0):
  • Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset (SWRST) bits
  • Recoverable Fault n Control registers (FCTRLA and FCTRLB)
  • Waveform Extension Control register (WEXCTRL)
  • Drive Control register (DRVCTRL)
  • Event Control register (EVCTRL)

Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the “Enable-Protected” property in the register description.

Before the TCC is enabled, it must be configured as outlined by the following steps:
  1. Enable the TCC bus clock (CLK_TCCx_APB).
  2. If Capture mode is required, enable the channel in Capture mode by writing a '1' to the Capture Enable bit in the Control A register (CTRLA.CPTEN).
Optionally, the following configurations can be set before enabling TCC:
  1. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER).
  2. Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC).
  3. If down-counting operation is desired, write the Counter Direction bit in the Control B Set register (CTRLBSET.DIR) to '1'.
  4. Select the Waveform Generation operation in the WAVE register (WAVE.WAVEGEN).
  5. Select the Waveform Output Polarity in the WAVE register (WAVE.POL).
  6. The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit group in the Driver register (DRVCTRL.INVEN).