55.20 DAC Module Electrical Specifications

Table 55-24. DAC Module Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
DAC_1DRESDAC Resolution12Bits
DAC_3DCLKInternal DAC Clock Frequency (GCLK_DAC)12MHz
DAC_5DSAMPDAC Sampling RateLow Power

DACCTRLn.CCTRL[1:0] =0

0.10.1 Msps+/-4LSB of final value for step size≤100Lsb at

CLOAD and RLOAD w/AVDD=3.3V

High Power

DACCTRLn.CCTRL[1:0] =2

0.11Msps
DAC_7VOUTOutput Voltage Linear RangeAVSS+0.15 AVDD-0.15VExt Pin(Buffered)

VREF=AVDD at CLOAD and RLOAD

AVSS+0.15VREFVExt Pin(Buffered)

VREF ≤ AVDD-150mV at CLOAD and RLOAD

AVSSVREFVInternal connection to another module (eg AC) (No buffer)
DAC_9VREF (1,2)DAC Reference Input Option REFSEL=VREFAB

CTRLB.REFSEL[1:0] =0x2

2.4VAVDD-0.15V External Reference VREFAB (buffered)

VREF bypass Cap = 0.01µF

REFSEL=VREFAU

CTRLB.REFSEL[1:0] =0x0

AVDDVExternal Reference VREFAU (unbuffered)

VREF bypass Cap = 0.01µF

REFSEL=INTREF

CTRLB.REFSEL[1:0] =0x3

VR_1

VR_3

AVDD-0.15VInternal Reference

VR_1, VR_3: Refer to

Internal Voltage Reference Electrical Specifications

REFSEL=AVDD

CTRLB.REFSEL[1:0] =0x1

AVDDV
DAC_11CLOADDAC Out max load to meet VOUT and TSET 50pF
DAC_13RLOADDAC Out max load to meet VOUT and TSET 5kΩ
DAC_15TSET (6)DAC Settling TimeLow Power / REFSEL=AVDD

DACCTRLn.CCTRL[1:0]=0

(1/DSAMPmin) +1µs+/-4LSB of final value for step size≤100Lsb at

CLOAD and RLOAD w/AVDD=3.3V

High Performance / REFSEL=AVDD

DACCTRLn.CCTRL[1:0] = 2

(1/DSAMPmin) +1µs+/-4LSB of final value for step size≤100Lsb at

CLOAD and RLOAD w/AVDD = 3.3V

DAC_17TSET_FS(6)DAC Full Scale Settling TimeLow Power / REFSEL=AVDD

DACCTRLn.CCTRL[1:0] = 0

(7/DSAMPmin) +1µs+/-4LSB of final value for step size from 10% to 90% at

CLOAD and RLOAD w/AVDD = 3.3V

High-Performance/REFSEL= AVDD

DACCTRLn.CCTRL[1:0] = 2

(7/DSAMPmin) +1µs+/-4LSB of final value for step size from 10% to 90% at

CLOAD and RLOAD w/AVDD = 3.3V

DIFFERENTIAL MODE (1,2,4,5)
DDAC_19INLIntegral Non Linearity-3.43.4LSB 1Msps, External VREF REFSEL= VREFAB = 2.4V

CTRLB.REFSEL[1:0] = 0x2,

AVDD = VDD = 3.3V w/ CLOAD and RLOAD.

DDAC_21DNLDifferential Non Linearity-3.63.6LSB
DDAC_23GERR Gain Error-69.769.7 LSB
DDAC_25EOFF Offset Error-68.368.3 LSB1Msps, External VREF REFSEL= VREFAB= 2.4V

CTRLB.REFSEL[1:0] = 0x2,

AVDD = VDD = 3.3V w/ CLOAD and RLOAD.

DDAC_27ENOB(7)Effective Number of Bit9.9Bits 1Msps, External VREF REFSEL= VREFAB = 2.4V

CTRLB.REFSEL[1:0] = 0x2,

AVDD = VDD = 3.3V w/ CLOAD and RLOAD.

DDAC_29SNR(7)Signal To Noise Ratio63.5db
DDAC_31THD (3,7)Total Harmonic Distortion-61db
SINGLE ENDED MODE (1,2,4,5)
SDAC_19INLIntegral Non Linearity-44LSB 1Msps, External VREF REFSEL= VREFAB = 2.4V

CTRLB.REFSEL[1:0] = 0x2,

AVDD = VDD = 3.3V w/ CLOAD and RLOAD.

SDAC_21DNLDifferential Non Linearity-6.16.1LSB
SDAC_23GERR Gain Error-61.561.5 LSB
SDAC_25EOFFOffset Error-35.935.9 LSB1Msps, External VREF REFSEL= VREFAB = 2.4V

CTRLB.REFSEL[1:0] = 0x2,

AVDD = VDD = 3.3V w/ CLOAD and RLOAD.

SDAC_27ENOB(7)Effective Number of Bit9.1Bits 1Msps, External VREF REFSEL= VREFAB = 2.4V

CTRLB.REFSEL[1:0] = 0x2,

AVDD = VDD = 3.3V w/ CLOAD and RLOAD.

SDAC_29SNR(7)Signal To Noise Ratio63.5dB
SDAC_31THD (3,7)Total Harmonic Distortion-61dB
Note:
  1. DAC reference voltages < 2.4V, is not practical and peripheral performance is not guaranteed.
  2. DAC functional device operation with external VREF<2.4V is guaranteed, but not characterized. DAC will function, but with degraded performance. DAC accuracy is limited by users application noise/accuracy on AVDD, AVSS and VREF accuracy/drift.
  3. Value taken over 7 harmonics.
  4. 12-bit mode.
  5. Over VOUT range defined by DAC_7 parameter.
  6. Assuming DAC is configured and that first conversion is done.
  7. Characterized with 15 kHz sine wave and low pass filter at 250 kHz.