55.20 DAC Module Electrical Specifications
AC CHARACTERISTICS | Standard Operating
Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial Temperature |
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Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions | |
DAC_1 | DRES | DAC Resolution | — | — | 12 | Bits | — | |
DAC_3 | DCLK | Internal DAC Clock Frequency (GCLK_DAC) | — | — | 12 | MHz | — | |
DAC_5 | DSAMP | DAC Sampling Rate | Low Power DACCTRLn.CCTRL[1:0] =0 |
0.1 | — | 0.1 | Msps | +/-4LSB of final value for step
size≤100Lsb at CLOAD and RLOAD w/AVDD=3.3V |
High Power DACCTRLn.CCTRL[1:0] =2 |
0.1 | — | 1 | Msps | ||||
DAC_7 | VOUT | Output Voltage Linear Range | AVSS+0.15 | — | AVDD-0.15 | V | Ext Pin(Buffered) VREF=AVDD at CLOAD and RLOAD |
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AVSS+0.15 | — | VREF | V | Ext Pin(Buffered) VREF ≤ AVDD-150mV at CLOAD and RLOAD |
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AVSS | — | VREF | V | Internal connection to another module (eg AC) (No buffer) | ||||
DAC_9 | VREF (1,2) | DAC Reference Input Option | REFSEL=VREFAB CTRLB.REFSEL[1:0] =0x2 |
2.4V | — | AVDD-0.15 | V | External Reference VREFAB (buffered) VREF bypass Cap = 0.01µF |
REFSEL=VREFAU CTRLB.REFSEL[1:0] =0x0 |
— | AVDD | V | External Reference VREFAU (unbuffered) VREF bypass Cap = 0.01µF |
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REFSEL=INTREF CTRLB.REFSEL[1:0] =0x3 |
VR_1 VR_3 |
AVDD-0.15 | V | Internal Reference VR_1, VR_3: Refer to |
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REFSEL=AVDD CTRLB.REFSEL[1:0] =0x1 |
— | AVDD | V | — | ||||
DAC_11 | CLOAD | DAC Out max load to meet VOUT and TSET | — | — | 50 | pF | — | |
DAC_13 | RLOAD | DAC Out max load to meet VOUT and TSET | 5 | — | — | kΩ | — | |
DAC_15 | TSET (6) | DAC Settling Time | Low Power / REFSEL=AVDD
DACCTRLn.CCTRL[1:0]=0 |
— | — | (1/DSAMPmin) +1 | µs | +/-4LSB of final value for step size≤100Lsb at
CLOAD and RLOAD w/AVDD=3.3V |
High Performance / REFSEL=AVDD
DACCTRLn.CCTRL[1:0] = 2 |
— | — | (1/DSAMPmin) +1 | µs | +/-4LSB of final value for step size≤100Lsb at
CLOAD and RLOAD w/AVDD = 3.3V |
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DAC_17 | TSET_FS(6) | DAC Full Scale Settling Time | Low Power / REFSEL=AVDD DACCTRLn.CCTRL[1:0] = 0 |
— | — | (7/DSAMPmin) +1 | µs | +/-4LSB of final value for step size from 10% to 90%
at CLOAD and RLOAD w/AVDD = 3.3V |
High-Performance/REFSEL= AVDD DACCTRLn.CCTRL[1:0] = 2 |
— | — | (7/DSAMPmin) +1 | µs | +/-4LSB of final value for step size from 10% to 90%
at CLOAD and RLOAD w/AVDD = 3.3V |
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DIFFERENTIAL MODE (1,2,4,5) | ||||||||
DDAC_19 | INL | Integral Non Linearity | -3.4 | — | 3.4 | LSB | 1Msps, External VREF REFSEL= VREFAB =
2.4V CTRLB.REFSEL[1:0] = 0x2, AVDD = VDD = 3.3V w/ CLOAD and RLOAD. |
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DDAC_21 | DNL | Differential Non Linearity | -3.6 | — | 3.6 | LSB | ||
DDAC_23 | GERR | Gain Error | — | -69.7 | — | 69.7 | LSB | |
DDAC_25 | EOFF | Offset Error | — | -68.3 | — | 68.3 | LSB | 1Msps, External VREF REFSEL= VREFAB= 2.4V
CTRLB.REFSEL[1:0] = 0x2, AVDD = VDD = 3.3V w/ CLOAD and RLOAD. |
DDAC_27 | ENOB(7) | Effective Number of Bit | 9.9 | — | — | Bits | 1Msps, External VREF REFSEL= VREFAB =
2.4V CTRLB.REFSEL[1:0] = 0x2, AVDD = VDD = 3.3V w/ CLOAD and RLOAD. |
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DDAC_29 | SNR(7) | Signal To Noise Ratio | 63.5 | — | — | db | ||
DDAC_31 | THD (3,7) | Total Harmonic Distortion | — | — | -61 | db | ||
SINGLE ENDED MODE (1,2,4,5) | ||||||||
SDAC_19 | INL | Integral Non Linearity | -4 | — | 4 | LSB | 1Msps, External VREF REFSEL= VREFAB =
2.4V CTRLB.REFSEL[1:0] = 0x2, AVDD = VDD = 3.3V w/ CLOAD and RLOAD. |
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SDAC_21 | DNL | Differential Non Linearity | -6.1 | — | 6.1 | LSB | ||
SDAC_23 | GERR | Gain Error | — | -61.5 | — | 61.5 | LSB | |
SDAC_25 | EOFF | Offset Error | — | -35.9 | — | 35.9 | LSB | 1Msps, External VREF REFSEL= VREFAB = 2.4V
CTRLB.REFSEL[1:0] = 0x2, AVDD = VDD = 3.3V w/ CLOAD and RLOAD. |
SDAC_27 | ENOB(7) | Effective Number of Bit | 9.1 | — | — | Bits | 1Msps, External VREF REFSEL= VREFAB =
2.4V CTRLB.REFSEL[1:0] = 0x2, AVDD = VDD = 3.3V w/ CLOAD and RLOAD. |
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SDAC_29 | SNR(7) | Signal To Noise Ratio | 63.5 | — | — | dB | ||
SDAC_31 | THD (3,7) | Total Harmonic Distortion | — | — | -61 | dB | ||
Note:
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