39.5.2 Clocks

The PCC bus clock (CLK_APB_PCC) is provided by the Main Clock Controller (MCLK) through the AHB-APB D bridge. The clock is enabled and disabled by writing the PCC bit the in the APB D Mask register (MCLK.APBDMASK.PCC).

For capturing operation, the external device has to provide a PCC clock signal (PCC_CLK) synchronous to the data received (pixel clock) through a pin. Refer to the PORT section and the Pinout table for additional information.

Writing any of the registers does not require the PCC_CLK to be enabled.