38.8.7 CC Control

Name: CCCR
Offset: 0x18
Reset: 0x00000001
Property: Read-only, Write-restricted

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  TXPEFBIPXHD  BRSEFDOE 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
 TESTDARMONCSRCSAASMCCEINIT 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000001 

Bit 14 – TXP Transmit Pause

This bit field is write-restricted and only writable if bit fields CCE = 1 and INIT = 1.
ValueDescription
0 Transmit pause disabled.
1 Transmit pause enabled. The CAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame.

Bit 13 – EFBI Edge Filtering during Bus Integration

ValueDescription
0 Edge filtering is disabled.
1 Two consecutive dominant tq required to detect an edge for hard synchronization.

Bit 12 – PXHD Protocol Exception Handling Disable

Note: When protocol exception handling is disabled, the CAN will transmit an error frame when it detects a protocol exception condition.
ValueDescription
0 Protocol exception handling enabled.
1 Protocol exception handling disabled.

Bit 9 – BRSE Bit Rate Switch Enable

Note: When CAN FD operation is disabled FDOE = 0, BRSE is not evaluated.
ValueDescription
0 Bit rate switching for transmissions disabled.
1 Bit rate switching for transmissions enabled.

Bit 8 – FDOE FD Operation Enable

ValueDescription
0 FD operation disabled.
1 FD operation enabled.

Bit 7 – TEST Test Mode Enable

This bit field is write-restricted.

Writing a 0 to this field is always allowed.

Writing a 1 to this field is only allowed if bit fields CCE = 1 and INIT = 1.

ValueDescription
0 Normal operation. Register TEST holds reset values.
1 Test Mode, write access to register TEST enabled.

Bit 6 – DAR Disable Automatic Retransmission

This bit field is write-restricted and only writable if bit fields CCE = 1 and INIT = 1.

ValueDescription
0 Automatic retransmission of messages not transmitted successfully enabled.
1 Automatic retransmission disabled.

Bit 5 – MON Bus Monitoring Mode

This bit field is write-restricted.

Writing a 0 to this field is always allowed.

Writing a 1 to this field is only allowed if bit fields CCE = 1 and INIT = 1.

ValueDescription
0 Bus Monitoring Mode is disabled.
1 Bus Monitoring Mode is enabled.

Bit 4 – CSR Clock Stop Request

ValueDescription
0 No clock stop is requested.
1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.

Bit 3 – CSA Clock Stop Acknowledge

ValueDescription
0 No clock stop acknowledged.
1 CAN may be set in power down by stopping CLK_CAN_APB and GCLK_CAN.

Bit 2 – ASM Restricted Operation Mode

This bit field is write-restricted.

Writing a 0 to this field is always allowed.

Writing a 1 to this field is only allowed if bit fields CCE = 1 and INIT = 1.

ValueDescription
0 Normal CAN operation.
1 Restricted Operation Mode active.

Bit 1 – CCE Configuration Change Enable

This bit field is write-restricted and only writable if bit field INIT = 1.

ValueDescription
0 The CPU has no write access to the protected configuration registers.
1 The CPU has write access to the protected configuration registers (while CCCR.INIT = 1).

Bit 0 – INIT Initialization

Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. The programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.

ValueDescription
0 Normal Operation.
1 Initialization is started.