10.3.3 SRAM Quality of Service
To ensure that Hosts with latency requirements get sufficient priority when accessing RAM, priority levels can be assigned to the Hosts for different types of access.
The Quality of Service (QoS) level is independently selected for each Host accessing the RAM. For any access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in the table below.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
If a Host is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the Host and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the tables below for details.
The CPU QoS level can be written/read, using 32-bit access only, at address 0x4100C11C, bits [1:0]. Its reset value is 0x3.
The ICM QoS level can be written/read, using 32-bit access only, at address 0x4100C128, bits [1:0]. Its reset value is 0x1.
Refer to different Host QOS control registers for configuring QoS for the other Hosts (DSU, DMAC, CAN, USB).
| SRAM Port Connection | Port ID | Connection Type | QoS | default QoS |
|---|---|---|---|---|
| CM4 - Cortex M4 Processor | 0 | Bus Matrix | 0x4100C11C, bits[1:0](1) | 0x3 |
| DSU - Device Service Unit | 1 | Bus Matrix | IP-CFG.LQOS | 0x2 |
| DMAC - Direct Memory Access Controller - Data Access | 2 (WR), 3 (RD) | Bus Matrix | IP-PRICTRL0.QOSn | 0x2 |
| ICM - Integrity Check Monitor | 3 | Bus Matrix | 0x4100C128, bits[1:0](1) | 0x1 |
| DMAC - Direct Memory Access Controller - Fetch Access | 4, 5 | Direct | IP-PRICTRL0.QOSn | 0x2 |
| DMAC - Direct Memory Access Controller - Write-Back Access | 6, 7 | Direct | IP-PRICTRL0.QOSn | 0x2 |
| SDHC0 - SD/MMC Host Controller | 8 | Direct | STATIC-1 | 0x1 |
| SDHC1 - SD/MMC Host Controller | 9 | Direct | STATIC-1 | 0x1 |
| CAN0 - Control Area Network | 10 | Direct | IP-MRCFG.QOS | 0x1 |
| CAN1 - Control Area Network | 11 | Direct | IP-MRCFG.QOS | 0x1 |
| GMAC - Ethernet MAC | 12 | Direct | STATIC-2 | 0x2 |
| USB - Universal Serial Bus - Configuration Access | 13 | Direct | IP-QOSCTRL.CQOS | 0x3 |
| USB - Universal Serial Bus - Data Access | 13 | Direct | IP-QOSCTRL.DQOS | 0x3 |