55.39 PDEC Electrical Specifications

Figure 55-26. Position Decoder (PDEC) Counter Mode Timing Diagram
Figure 55-27. Position Decoder (PDEC) Input Timing Diagrams
Table 55-54. Quadrature Encoder Interface Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
PDEC_1 TtPH TPCK high time 2/fGCLK_PDEC — — ns FCLK_41: Refer to Maximum Clock Frequencies Electrical Specifications
PDEC_3 TtPL TPCK low time 2/fGCLK_PDEC — — ns
PDEC_5 TtPP TPCK input period 4/fGCLK_PDEC — — ns
PDEC_7 TCKEXTDLY Delay from External TxCK Clock Edge to counter Increment — — 4/fGCLK_PDEC ns
PDEC_11 TPDH Position Decoder Input High Time 4/fGCLK_PDEC — — ns
PDEC_13 TPDL Position Decoder Input Low Time 4/fGCLK_PDEC — — ns
PDEC_15 TPDIN Position Decoder Input Period 8/fGCLK_PDEC — — ns
PDEC_21 TPDFH Filter Time to Recognize High, with Digital Filter 4/fGCLK_PDEC — — ns
PDEC_23 TPDFL Filter Time to Recognize Low, with Digital Filter 4/fGCLK_PDEC — — ns
PDEC_24 fGCLK_PDEC GCLK_PDEC — — FCLK_41 MHz