33.7.1 Control A

This bit selects the data order when a character is shifted out from the shift register.

This bit is not synchronized.

In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.

This bit is not synchronized.

In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.

This bit is not synchronized.

This bit field selects the various frame formats supported by the SPI in Client mode. When the 'SPI frame with address' format is selected, the first byte received is checked against the ADDR register.

These bits define the data in (DI) pad configurations.

In Host operation, DI is MISO.

In Client operation, DI is MOSI.

These bits are not synchronized.

This bit defines the available pad configurations for data out (DO) and the serial clock (SCK).

In Client operation, the SPI Select (SS) line is controlled by DOPO (PAD[2]).

In Host operation, the SPI Select (SS) line is controlled by a GPIO driven by the application.

In Host operation, DO is MOSI.

In Client operation, DO is MISO.

These bits are not synchronized.

This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs.

This bit is not synchronized.

This bit defines the functionality in Standby Sleep mode.

These bits are not synchronized.

These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM.

0x2: SPI Client operation

0x3: SPI Host operation

These bits are not synchronized.

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not enable-protected.

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing ''1' to the CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Due to synchronization, there is a delay from writing the CTRLA.SWRST until the reset is complete. The CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete.